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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5634M Rev. 2, 12/2008
MPC5634M
144 LQFP 20 mm x 20 mm 100 LQFP 14 mm x 14 mm
MPC5634M Microcontroller Data Sheet
* Operating Parameters - Fully static operation, 0 MHz - 80 MHz (plus 2% frequency modulation - 82 MHz) - -40 C to 150 C junction temperature operating range - Low power design -Less than 400 mW power dissipation (nominal) -Designed for dynamic power management of core and peripherals -Software controlled clock gating of peripherals -Low power stop mode, with all clocks stopped - Fabricated in 90 nm process - 1.2 V internal logic * High performance e200z335 core processor * Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR) * Enhanced direct memory access (eDMA) controller * Interrupt controller (INTC) - 191 peripheral interrupt request sources, plus 165 reserved positions - Low latency--three clocks from receipt of interrupt request from peripheral to interrupt request to processor * Frequency Modulating Phase-locked loop (FMPLL) * Calibration bus interface (EBI) (available only in the calibration package) * System integration unit (SIU) centralizes control of pads, GPIO pins and external interrupts. * Error correction status module (ECSM) provides configurable error-correcting codes (ECC) reporting * Up to 1.5 MB on-chip flash memory * Up to 94 KB on-chip static RAM * Boot assist module (BAM) enables and manages the transition of MCU from reset to user code execution from internal flash memory, external memory on the calibration bus or download and execution of code via FlexCAN or eSCI. * Periodic interrupt timer (PIT)
176 LQFP 24 mm x 24 mm
208 MAPBGA 17 mm x 17 mm
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- 32-bit wide down counter with automatic reload - 4 channels clocked by system clock - 1 channel clocked by crystal clock System timer module (STM) - 32-bit up counter with 8-bit prescaler - Clocked from system clock - 4 channel timer compare hardware Software watchdog timer (SWT) 32-bit timer Enhanced modular I/O system (eMIOS) - 16 standard timer channels (up to 14 channels connected to pins in LQFP144) - 24-bit timer resolution Second-generation enhanced time processor unit (eTPU2) - High level assembler/compiler - Enhancements to make `C' compiler more efficient - New `engine relative' addressing mode Enhanced queued A/D converter (eQADC) - 2 independent on-chip RSD Cyclic ADCs - Up to 34 input channels available to the two on-chip ADCs - 4 pairs of differential analog input channels 2 deserial serial peripheral interface modules (DSPI) - SPI provides full duplex communication ports with interrupt and DMA request support - Deserial serial interface (DSI) achieves pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO 2 enhanced serial communication interface (eSCI) modules 2 FlexCAN modules Nexus port controller (NPC) per IEEE-ISTO 5001-2003 standard IEEE 1149.1 JTAG controller (JTAGC)
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved. Preliminary--Subject to Change Without Notice
Table of Contents
1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 MPC5634M Features . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 MPC5634M Feature Details . . . . . . . . . . . . . . . . . . . . .12 1.3.1 e200z335 Core . . . . . . . . . . . . . . . . . . . . . . . . .12 1.3.2 Crossbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.3.3 eDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.3.4 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . .14 1.3.5 FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.3.6 Calibration EBI. . . . . . . . . . . . . . . . . . . . . . . . . .15 1.3.7 SIU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3.8 ECSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.3.9 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.3.10 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.3.11 BAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.3.12 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.3.13 eTPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.3.14 eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.3.15 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.3.16 eSCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.3.17 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.3.18 System Timers. . . . . . . . . . . . . . . . . . . . . . . . . .25 1.3.19 Software Watchdog Timer (SWT) . . . . . . . . . . .26 1.3.20 Nexus Port Controller . . . . . . . . . . . . . . . . . . . .26 1.3.21 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.4 MPC5634M Series Architecture . . . . . . . . . . . . . . . . . .28 1.4.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.4.2 Block Summary . . . . . . . . . . . . . . . . . . . . . . . . .29 Pinout and Signal Description . . . . . . . . . . . . . . . . . . . . . . . .30 2.1 100 LQFP Pinout (all 100-pin devices) . . . . . . . . . . . . .30 2.2 144 LQFP Pinout (all 144-pin devices) . . . . . . . . . . . . .32 2.3 176 LQFP Pinout (MPC5634M) . . . . . . . . . . . . . . . . . .33 2.4 176 LQFP Pinout (MPC5633M) . . . . . . . . . . . . . . . . . .34 2.5 MAPBGA208 Ballmap (MPC5634M) . . . . . . . . . . . . . .35 3 2.6 MAPBGA208 Ballmap (MPC5633M only) . . . . . . . . . . 36 2.7 Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.1 General Notes for Specifications at Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . 56 3.3 EMI (Electromagnetic Interference) Characteristics . . 58 3.4 Electromagnetic Static Discharge (ESD) Characteristics59 3.5 Power Management Control (PMC) and Power On Reset (POR) Electrical Specifications . . . . . . . . . . . . . . . . . . 59 3.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . 61 3.7 DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . 62 3.7.1 I/O Pad Current Specifications . . . . . . . . . . . . . 68 3.7.2 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 69 3.8 Oscillator and PLLMRFM Electrical Characteristics . . 70 3.9 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 72 3.10 Platform Flash Controller Electrical Characteristics . . 73 3.11 Flash Memory Electrical Characteristics . . . . . . . . . . . 73 3.12 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.12.1 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 74 3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.13.1 IEEE 1149.1 Interface Timing . . . . . . . . . . . . . 77 3.13.2 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.13.3 Calibration Bus Interface Timing . . . . . . . . . . . 83 3.13.4 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.13.5 DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.13.6 eQADC SSI Timing . . . . . . . . . . . . . . . . . . . . . 92 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . 93 4.1 100 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.3 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.4 208 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Ordering Information . . . . . . . . . . . . . . . . . . . . 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MPC5634M Microcontroller Data Sheet, Rev. 2 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
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Overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5634M series of microcontroller units (MCUs). For functional characteristics, refer to the MPC5634M Microcontroller Reference Manual. The MPC5634M series microcontrollers are system-on-chip devices that are built on Power ArchitectureTM technology and: * * * * Are 100% user-mode compatible with the classic Power Architecture instruction set Contain enhancements that improve the architecture's fit in embedded applications Include additional instruction support for digital signal processing (DSP) Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system
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Device Comparison
Table 1. MPC5634M Device Summary
Feature Flash memory size (KB) Total RAM size (KB) Standby RAM size (KB) Processor core Core frequency (MHz) Calibration bus width
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MPC5634M 1536 94 32 32-bit e200z335 with SPE support 60/80 16 bits 32 16 Up to 343 2 2 2 Yes Channels Code memory (KB) 32 14 3 2 Yes 364
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MPC5633M 1024 64 24 32-bit e200z335 with SPE support 40/60/80 16 bits 32 16 Up to 343 2 2 2 Yes 32 14 3 2 Yes 364
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MPC5632M 768 48 24 32-bit e200z335 with SPE support 40/60 -- 32 8 Up to 323 2 2 2 Yes 32 14 3 2 Yes 3645 Yes Class 2+ Yes 5
DMA (direct memory access) channels eMIOS (enhanced modular input-output system) channels eQADC (enhanced queued analog-to-digital converter) channels eSCI (serial communication interface) DSPI (deserial serial peripheral interface) Microsecond Bus compatible interface eTPU (enhanced time processor unit)
Parameter RAM (KB) FlexCAN (controller area network)4 FMPLL (frequency-modulated phase-locked loop) INTC (interrupt controller) channels JTAG controller NDI (Nexus development interface) level Non-maskable interrupt and critical interrupt PIT (peripheral interrupt timers)
Yes Class 2+ Yes 5
Yes Class 2+ Yes 5
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3
Overview
Table 1. MPC5634M Device Summary (continued)
Feature Task monitor timer Temperature sensor Windowing software watchdog Packages MPC5634M 4 channels Yes Yes 144 LQFP 176 LQFP 208 MAPBGA MPC5633M 4 channels Yes Yes 100 LQFP6 144 LQFP 176 LQFP6 208 MAPBGA MPC5632M 4 channels Yes Yes 100 LQFP 144 LQFP
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Revision 1 of this device contains C90FL flash memory; revision 2 of this device contains LC flash memory. Calibration package only The 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23. One FlexCAN module has 64 message buffers; the other has 32 message buffers. 165 interrupt channels are reserved for compatibility with future devices. This device has 191 peripheral interrupt sources plus 8 software interrupts available to the user. Not available in Revision 1 of this device
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MPC5634M Features
Operating Parameters -- Fully static operation, 0 MHz - 80 MHz (plus 2% frequency modulation - 82 MHz) -- -40 C to 150 C junction temperature operating range -- Low power design - Less than 400 mW power dissipation (nominal) - Designed for dynamic power management of core and peripherals - Software controlled clock gating of peripherals - Low power stop mode, with all clocks stopped -- Fabricated in 90 nm process -- 1.2 V internal logic -- Single power supply (for 100- and 144-pin packages) with 5.0 V -10%/+5% (4.5 V to 5.25 V) with internal regulator to provide 3.3 V and 1.2 V for the core -- Input and output pins with 5.0 V -10%/+5% (4.5 V to 5.25 V) range - 35%/65% VDDE CMOS switch levels (with hysteresis) - Selectable hysteresis - Selectable slew rate control -- Calibration bus pins support 1.8 V to 3.3 V 10% (1.6 V to 3.6 V) operation - Selectable drive strength control - Nexus pins powered by 3.3 V supply (176 LQFP and 208 MAPBGA) or 5.0 V supply (other packages) - Selectable slew rate control - Fixed output voltage at 3.3 V - Unused pins configurable as GPIO or timed I/O -- Designed with EMI reduction techniques - Phase-locked loop - Frequency modulation of system clock frequency
MPC5634M Microcontroller Data Sheet, Rev. 2 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
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- On-chip bypass capacitance - Selectable slew rate and drive strength High performance e200z335 core processor -- 32-bit Power Architecture Book E programmer's model -- Variable Length Encoding Enhancements - Allows Power Architecture instruction set to be optionally encoded in a mixed 16 and 32-bit instructions - Results in smaller code size -- Single issue, 32-bit Power Architecture Book E compliant CPU -- In-order execution and retirement -- Precise exception handling -- Branch processing unit - Dedicated branch address calculation adder - Branch acceleration using Branch Lookahead Instruction Buffer -- Load/store unit - One-cycle load latency - Fully pipelined - Big and Little Endian support - Misaligned access support - Zero load-to-use pipeline bubbles -- Thirty-two 64-bit general purpose registers (GPRs) -- Memory management unit (MMU) with 8-entry fully-associative translation look-aside buffer (TLB) -- Separate instruction bus and load/store bus -- Vectored interrupt support -- Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to execution of first instruction of interrupt exception handler) -- Non-maskable interrupt (NMI) input for handling external events that must produce an immediate response, e.g., power down detection. On this device, the NMI input is connected to the Critical Interrupt Input. (May not be recoverable) -- Critical Interrupt input. For external interrupt sources that are higher priority than provided by the Interrupt Controller. (Always recoverable) -- New `Wait for Interrupt' instruction, to be used with new low power modes -- Reservation instructions for implementing read-modify-write accesses -- Signal processing extension (SPE) APU - Operating on all 32 GPRs that are all extended to 64 bits wide - Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including integer vector MAC and MUL operations) (SIMD) - Provides rich array of extended 64-bit loads and stores to/from extended GPRs - Fully code compatible with e200z6 core -- Floating point - IEEE 754 compatible with software wrapper - Scalar single precision in hardware, double precision with software library - Conversion instructions between single precision floating point and fixed point - Fully code compatible with e200z6 core -- Long cycle time instructions, except for guarded loads, do not increase interrupt latency -- Extensive system development support through Nexus debug port Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
MPC5634M Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary--Subject to Change Without Notice
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Overview
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-- Three master ports, four slave ports - Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA - Slave: Flash; SRAM; Peripheral Bridge; calibration EBI -- 32-bit internal address bus, 64-bit internal data bus Enhanced direct memory access (eDMA) controller -- 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers -- Supports variable sized queues and circular queues -- Source and destination address registers are independently configured to post-increment or remain constant -- Each transfer is initiated by a peripheral, CPU, or eDMA channel request -- Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer Interrupt controller (INTC) -- 191 peripheral interrupt request sources -- 8 software setable interrupt request sources -- 9-bit vector - Unique vector for each interrupt request source - Provided by hardware connection to processor or read from register -- Each interrupt source can be programmed to one of 16 priorities -- Preemption - Preemptive prioritized interrupt requests to processor - ISR at a higher priority preempts ISRs or tasks at lower priorities - Automatic pushing or popping of preempted priority to or from a LIFO - Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources. -- Low latency--three clocks from receipt of interrupt request from peripheral to interrupt request to processor Frequency Modulating Phase-locked loop (FMPLL) -- Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution -- Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency without forcing the FMPLL to re-lock -- System clock divider (SYSDIV) for reducing the system clock frequency in normal or bypass mode -- Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and from 4 MHz to 16 MHz at the FMPLL input -- Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz -- VCO free-running frequency range from 25 MHz to 125 MHz -- Four bypass modes: crystal or external reference with PLL on or off -- Two normal modes: crystal or external reference -- Programmable frequency modulation - Triangle wave modulation - Register programmable modulation frequency and depth -- Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions - User-selectable ability to generate an interrupt request upon loss of lock - User-selectable ability to generate a system reset upon loss of lock -- Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference and output clocks - User-selectable ability to generate an interrupt request upon loss of clock
MPC5634M Microcontroller Data Sheet, Rev. 2 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
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- User-selectable ability to generate a system reset upon loss of clock - Backup clock (reference clock or FMPLL free-running) can be applied to the system in case of loss of clock Calibration bus interface (EBI) -- Available only in the calibration package -- 1.8 V to 3.3 V 10% I/O (1.6 V to 3.6 V) -- Memory controller with support for various memory types -- 16-bit data bus, up to 22-bit address bus -- Selectable drive strength -- Configurable bus speed modes -- Bus monitor -- Configurable wait states System integration unit (SIU) -- Centralized GPIO control of 71 I/O pins -- Centralized pad control on a per-pin basis - Pin function selection - Configurable weak pull-up or pull-down - Drive strength - Slew rate - Hysteresis -- System reset monitoring and generation -- External interrupt inputs, filtering and control -- Critical Interrupt control -- Non-Maskable Interrupt control -- Internal multiplexer subblock (IMUX) - Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals) - Allows selection of interrupt requests between external pins and DSPI Error correction status module (ECSM) -- Configurable error-correcting codes (ECC) reporting On-chip flash memory -- Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface -- 16 KB shadow block -- Fetch Accelerator - Provide single cycle flash access @ 80 MHz - Quadruple 128-bit wide prefetch/burst buffers - Prefetch buffers can be configured to prefetch code or data or both -- Censorship protection scheme to prevent flash content visibility -- Flash divided into two independent 512 KB arrays, allowing reading from one array while erasing/programming the other array (used for EEPROM emulation) -- Memory block: - For MPC5634M: 18 blocks (4 x 16 KB, 2 x 32 KB, 2 x 64 KB, 10x 128 KB) - For MPC5633M: 14 blocks (4 x 16 KB, 2 x 32 KB, 2 x 64 KB, 6x 128 KB)1 - For MPC5632M: 12 blocks (4 x 16 KB, 2 x 32 KB, 2 x 64 KB, 4x 128 KB) -- Hardware programming state machine
1. Revision 1 of the MPC5633M has a different flash memory organization: 10 blocks (2 x 16 KB, 2 x 48 KB, 2 x 64 KB, 2 x 128 KB, 2 x 256 KB). MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
Overview
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On-chip static RAM -- For MPC5634M: 94 KB general purpose RAM of which 32 KB are on standby power supply -- For MPC5633M: 64 KB general purpose RAM of which 24 KB are on standby power supply1 -- For MPC5632M: 48 KB general purpose RAM of which 24 KB are on standby power supply Boot assist module (BAM) -- Enables and manages the transition of MCU from reset to user code execution in the following configurations: - Execution from internal flash memory - Execution from external memory on the calibration bus - Download and execution of code via FlexCAN or eSCI Periodic interrupt timer (PIT) -- 32-bit wide down counter with automatic reload -- Four channels clocked by system clock -- One channel clocked by crystal clock -- Each channel can produce periodic software interrupt -- Each channel can produce periodic triggers for eQADC queue triggering -- One channel out of the five can be used as wake-up timer to wake device from low power stop mode System timer module (STM) -- 32-bit up counter with 8-bit prescaler -- Clocked from system clock -- Four-channel timer compare hardware -- Each channel can generate a unique interrupt request -- Designed to address AutoSAR task monitor function Software watchdog timer (SWT) -- 32-bit timer -- Clock by system clock or crystal clock -- Can generate either system reset or non-maskable interrupt followed by system reset -- Enabled out of reset Enhanced modular I/O system (eMIOS) -- 16 standard timer channels (up to 14 channels connected to pins in 144 LQFP) -- 24-bit timer resolution -- Supports a subset of the timer modes found in eMIOS on MPC5554 -- 3 selectable time bases plus shared time or angle counter bus -- DMA and interrupt request support -- Motor control capability Second-generation enhanced time processor unit (eTPU2) -- High level assembler/compiler -- Enhancements to make `C' compiler more efficient -- New `engine relative' addressing mode -- 32 channels (each channel has dedicated I/O pin in all packages except 100 LQFP) -- 24-bit timer resolution -- Time base for the eTPU can be run at full system speed -- 14 KB code memory and 3 KB data memory -- Variable number of parameters allocatable per channel
1. Revision 1 of the MPC5633M has a different RAM organization: 48 KB general-purpose RAM, of which 24 KB are on the standby power supply. MPC5634M Microcontroller Data Sheet, Rev. 2 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
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Double match/capture channels Angle clock hardware support Nexus Class 1 Debug support Enhancements to make DMA and interrupt operation more flexible New programmable channel mode, for increased flexibility of channel hardware Scheduler priority-passing mechanism can be disabled New Watchdog mechanism kills threads over a programmable timeout New counter allows microengine load information collection for performance analysis Channels 1 and 2 (besides channel 0) can now be selected to control the EAC Timebase prescalers are now reset when the GTBE input is negated, guaranteeing synchronization with eMIOS in all cases -- New MISC flag indicates when an SCM signature calculation round is completed. This allows measuring of the average MISC scan period in a real application situation -- New channel TCCEA flag allows continuous capture even after TDLA is set, making it fully compatible with TPU behavior -- New branch condition PRSS tells the pin state at the time when a channel (match or transition) service request occurred -- MRLEA/B can now be negated independently by microcode -- New Engine Relative address mode allows a function to access SDM address space common to one engine, but distinct between engines Enhanced queued A/D converter (eQADC) -- Two independent on-chip RSD Cyclic ADCs - 8-, 10-, and 12-bit resolution - Differential conversions - Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK=7.5 MHz) and 8-bit accuracy at 1 MSample/s (ADC_CLK=15 MHz) for differential conversions - Differential channels include variable gain amplifier for improved dynamic range (x1; x2; x4) - Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 k; 100 k; low value of 5 k) - Single-ended signal range from 0 to 5 V - Sample times of 2 (default), 8, 64 or 128 ADC clock cycles - Provides time stamp information when requested - Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs (RFIFOs) - Supports both right-justified unsigned and signed formats for conversion results - Temperature sensor to enable measurement of die temperature - Ability to measure all power supply pins directly -- Automatic application of ADC calibration constants - Provision of reference voltages (25% VREF and 75% VREF) for ADC calibration purposes -- Up to 341 input channels available to the two on-chip ADCs -- Four pairs of differential analog input channels -- Full duplex synchronous serial interface to an external device - Has a free-running clock for use by the external device - Supports a 26-bit message length
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1.176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9
Overview
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- Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers, or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are full -- Parallel Side Interface to communicate with an on-chip companion module -- Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be aborted and the queued conversions in the CBUFFER to be bypassed. Delay from Trigger to start of conversion s 13 system clocks + 1 ADC clock.) -- eQADC Result Streaming. Generation of a continuous stream of ADC conversion results from a single eQADC command word. Controlled by two different trigger signals; one to define the rate at which results are generated and the other to define the beginning and ending of the stream. Used to digitize waveforms during specific time/angle windows, e.g., engine knock sensor sampling. -- Angular Decimation. The ability of the eQADC to sample an analog waveform in the time domain, perform FIR/IIR filtering also in the time domain, but to down sample the results in the angle domain. Resulting in a time domain filtered result at a given engine angle. -- Priority Based CFIFOs - Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served first. - Supports software and several hardware trigger modes to arm a particular CFIFO - Generates interrupt when command coherency is not achieved -- External Hardware Triggers - Supports rising edge, falling edge, high level and low level triggers - Supports configurable digital filter -- Supports four external 8-to-1 muxes which can expand the input channel number from 31 to 59 Two deserial serial peripheral interface modules (DSPI) -- SPI - Full duplex communication ports with interrupt and DMA request support - Supports all functional modes from QSPI subblock of QSMCM (MPC5xx family) - Support for queues in RAM - 6 chip selects, expandable to 64 with external demultiplexers - Programmable frame size, baud rate, clock delay and clock phase on a per frame basis - Modified SPI mode for interfacing to peripherals with longer setup time requirements - LVDS option for output clock and data to allow higher speed communication -- Deserial serial interface (DSI) - Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO - 32 bits per DSPI module - Triggered transfer control and change in data transfer control (for reduced EMI) - Compatible with Microsecond Bus Version 1.0 downlink Two enhanced serial communication interface (eSCI) modules -- UART mode provides NRZ format and half or full duplex interface -- eSCI bit rate up to 1 Mbps -- Advanced error detection, and optional parity generation and detection -- Word length programmable as 8, 9, 12 or 13 bits -- Separately enabled transmitter and receiver -- LIN support -- DMA support -- Interrupt request support
MPC5634M Microcontroller Data Sheet, Rev. 2
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Preliminary--Subject to Change Without Notice
Freescale Semiconductor
Overview
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-- Programmable clock source: system clock or oscillator clock -- Support Microsecond Bus (Timed Serial Bus - TSB) uplink Version 1.0 Two FlexCAN -- One with 32 message buffers; the second with 64 message buffers -- Full implementation of the CAN protocol specification, Version 2.0B -- Based on and including all existing features of the Freescale TouCAN module -- Programmable acceptance filters -- Short latency time for high priority transmit messages -- Arbitration scheme according to message ID or message buffer number -- Listen only mode capabilities -- Programmable clock source: system clock or oscillator clock -- Message buffers may be configured as mailboxes or as FIFO Nexus port controller (NPC) -- Per IEEE-ISTO 5001-2003 -- Real time development support for Power Architecture core and eTPU engine through Nexus class 2/1 -- Read and write access (Nexus class 3 feature that is supported on this device) - Run-time access of entire memory map - Calibration -- Support for data value breakpoints / watchpoints - Run-time access of entire memory map - Calibration Table constants calibrated using MMU and internal and external RAM Scalar constants calibrated using cache line locking -- Configured via the IEEE 1149.1 (JTAG) port IEEE 1149.1 JTAG controller (JTAGC) -- IEEE 1149.1-2001 Test Access Port (TAP) interface -- 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions -- 5-bit instruction register that supports additional public instructions -- Three test data registers: a bypass register, a boundary scan register, and a device identification register -- Censorship disable register. By writing the 64-bit serial boot password to this register, Censorship may be disabled until the next reset -- TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry On-chip Voltage Regulator for single 5 V supply operation -- On-chip regulator 5 V to 3.3 V for internal supplies -- On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core logic Low-power modes -- SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz), with modules (including the PLL) selectively disabled in software -- STOP Mode. System clock stopped to all modules including the CPU. Wake-up timer used to restart the system clock after a predetermined time
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
Overview
1.3
1.3.1
MPC5634M Feature Details
e200z335 Core
The e200z335 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 32x32 Hardware Multiplier array, result feed-forward hardware, and support hardware for division. Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into an instruction buffer capable of holding six instructions. Branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the instruction decode stage, allowing the branch target to be prefetched early. When a branch is detected at the instruction buffer, a prediction may be made on whether the branch is taken or not. If the branch is predicted to be taken, a target fetch is initiated and its target instructions are placed in the instruction buffer following the branch instruction. Many branches take zero cycle to execute by using branch folding. Branches are folded out from the instruction execution pipe whenever possible. These include unconditional branches and conditional branches with condition codes that can be resolved early. Conditional branches which are not taken and not folded execute in a single clock. Branches with successful target prefetching which are not folded have an effective execution time of one clock. All other taken branches have an execution time of two clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases. The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. The hardware floating-point unit utilizes the IEEE-754 single-precision floating-point format and supports single-precision floating-point operations in a pipelined fashion. The general purpose register file is used for source and destination operands, thus there is a unified storage model for single-precision floating-point data types of 32 bits and the normal integer type. Single-cycle floating-point add, subtract, multiply, compare, and conversion operations are provided. Divide instructions are multi-cycle and are not pipelined. The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware SIMD operations and supports a full complement of dual integer arithmetic operation including Multiply Accumulate (MAC) and dual integer multiply (MUL) in a pipelined fashion. The general purpose register file is enhanced such that all 32 of the GPRs are extended to 64 bits wide and are used for source and destination operands, thus there is a unified storage model for 32 x 32 MAC operations which generate greater than 32-bit results. The majority of both scalar and vector operations (including MAC and MUL) are executed in a single clock cycle. Both scalar and vector divides take multiple clocks. The SPE APU also provides extended load and store operations to support the transfer of data to and from the extended 64-bit GPRs. This SPE APU is fully binary compatible with e200z6 SPE APU used in MPC5554 and MPC5553.
MPC5634M Microcontroller Data Sheet, Rev. 2 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This enables the classic Power Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16- and 32-bit instructions. This results in a significantly smaller code size footprint without noticeably affecting performance. The classic Power Architecture instruction set and VLE instruction set are available concurrently. Regions of the memory map are designated as PPC or VLE using an additional configuration bit in each of Table Look-aside Buffers (TLB) entries in the MMU. The CPU core is enhanced by the addition of two additional interrupt sources; Non-Maskable Interrupt and Critical Interrupt. These two sources are routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing completely the Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled, except by reset. The non-maskable Interrupt is, as the name suggests, completely un-maskable and when asserted will always result in the immediate execution of the respective interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable. The Critical Interrupt is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the CPU and is guaranteed to be recoverable (code execution may be resumed from where it stopped). The CPU core has an additional `Wait for Interrupt' instruction that is used in conjunction with low power STOP mode. When Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.
1.3.2
Crossbar
The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and four slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows three concurrent transactions to occur from the master ports to any slave port; but each master must access a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features: * 3 master ports: -- e200z335 core complex Instruction port -- e200z335 core complex Load/Store port -- eDMA 4 slave ports -- FLASH -- calibration bus -- SRAM -- Peripheral bridge A/B (eTPU, eMIOS, SIU, DSPI, eSCI, FlexCAN, eQADC, BAM, decimation filter, PIT, STM and SWT) 32-bit internal address, 64-bit internal data paths
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1.3.3
eDMA
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 32 programmable channels, with minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA module provides the following features: * * * All data movement via dual-address transfers: read from source, write to destination Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes Transfer control descriptor organized to support two-deep, nested transfer operations
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13
Overview
* * *
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An inner data transfer loop defined by a "minor" byte transfer count An outer data transfer loop defined by a "major" iteration count Channel activation via one of three methods: -- Explicit software initiation -- Initiation via a channel-to-channel linking mechanism for continuous transfers -- Peripheral-paced hardware requests (one per channel) Support for fixed-priority and round-robin channel arbitration Channel completion reported via optional interrupt requests 1 interrupt per channel, optionally asserted at completion of major iteration count Error termination interrupts are optionally enabled Support for scatter/gather DMA processing Channel transfers can be suspended by a higher priority channel
1.3.4
Interrupt Controller
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. The INTC allows interrupt request servicing from up to 191 peripheral interrupt request sources, plus 165 sources reserved for compatibility with other family members). For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. Multiple processors can assert interrupt requests to each other through software setable interrupt requests. These same software setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a software setable interrupt request to finish the servicing in a lower priority ISR. Therefore these software setable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following features: * * * * * * * * * * * 356 peripheral interrupt request sources 8 software setable interrupt request sources 9-bit vector addresses Unique vector for each interrupt request source Hardware connection to processor or read from register Each interrupt source can be programmed to one of 16 priorities Preemptive prioritized interrupt requests to processor ISR at a higher priority preempts executing ISRs or tasks at lower priorities Automatic pushing or popping of preempted priority to or from a LIFO Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources Low latency--three clocks from receipt of interrupt request from peripheral to interrupt request to processor
This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.
MPC5634M Microcontroller Data Sheet, Rev. 2 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
1.3.5
FMPLL
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable. The PLL has the following major features: * * * * Input clock frequency from 4 MHz to 20 MHz Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in system clock frequencies from 16 MHz to 80 MHz with granularity of 4 MHz or better Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock 3 modes of operation -- Bypass mode with PLL off -- Bypass mode with PLL running (default mode out of reset) -- PLL normal mode Each of the three modes may be run with a crystal oscillator or an external clock reference Programmable frequency modulation -- Modulation enabled/disabled through software -- Triangle wave modulation up to 100 kHz modulation frequency -- Programmable modulation depth (0% to 2% modulation depth) -- Programmable modulation frequency dependent on reference frequency Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions Clock Quality Module -- detects the quality of the crystal clock and cause interrupt request or system reset if error is detected -- detects the quality of the PLL output clock. If an error is detected, causes a system reset or switches the system clock to the crystal clock and causes an interrupt request Programmable interrupt request or system reset on loss of lock Self-clocked mode (SCM) operation
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1.3.6
Calibration EBI
The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the VertiCal connector in the calibration address space. The Calibration EBI is only available in the VertiCal Calibration System. The Calibration EBI includes a memory controller that generates interface signals to support a variety of external memories. The Calibration EBI memory controller supports legacy flash, SRAM, and asynchronous memories. In addition, the calibration EBI supports up to three regions via chip selects (two chip selects are multiplexed with two address bits), along with programmed region-specific attributes. The calibration EBI supports the following features: * * * 22-bit address bus (two most significant signals multiplexed with two chip selects) 16-bit data bus Multiplexed mode with addresses and data signals present on the data lines
NOTE
The calibration EBI must be configured in multiplexed mode when the extended Nexus trace is used on the VertiCal Calibration System. This is because Nexus signals and address lines of the calibration bus share the same balls in the calibration package. * Memory controller with support for various memory types: -- Asynchronous/legacy flash and SRAM -- Most standard memories used with the MPC5xx or MPC55xx family Bus monitor
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15
*
Overview
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-- User selectable -- Programmable time-out period (with 8 external bus clock resolution) Configurable wait states (via chip selects) 3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant address signals) 2 write/byte enable (WE[0:1]/BE[0:1]) signals Configurable bus speed modes -- system frequency -- 1/2 of system frequency -- 1/4 of system frequency Optional automatic CLKOUT gating to save power and reduce EMI Compatible with MPC5xx external bus (with some limitations) Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF
1.3.7
SIU
The MPC5634M SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z335 CPU core is via the crossbar switch. The SIU provides the following features: * System configuration -- MCU reset configuration via external pins -- Pad configuration control for each pad -- Pad configuration control for virtual I/O via DSPI serialization System reset monitoring and generation -- Power-on reset support -- Reset status register provides last reset source to software -- Glitch detection on reset input -- Software controlled reset assertion External interrupt -- 11 interrupt requests -- Rising or falling edge event detection -- Programmable digital filter for glitch rejection -- Critical Interrupt request -- Non-Maskable Interrupt request GPIO -- GPIO function on 71 I/O pins -- Virtual GPIO on 64 I/O pins via DSPI serialization (requires external deserialization device) -- Dedicated input and output registers for setting each GPIO and Virtual GPIO pin Internal multiplexing -- Allows serial and parallel chaining of DSPIs -- Allows flexible selection of eQADC trigger inputs -- Allows selection of interrupt requests between external pins and DSPI
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MPC5634M Microcontroller Data Sheet, Rev. 2 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
1.3.8
ECSM
The error correction status module provides status information regarding platform memory errors reported by error-correcting codes.
1.3.9
Flash
The MPC5634M provides up to 1.5 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash module includes a Fetch Accelerator, that optimizes the performance of the flash array to match the CPU architecture and provides single cycle random access to the flash @ 80 MHz. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU `loads', DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer hits allow no-wait responses. Normal flash array accesses are registered and are forwarded to the system bus on the following cycle, incurring three wait-states. Prefetch operations may be automatically controlled, and are restricted to instruction fetch. The flash memory provides the following features: * * Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported. Fetch Accelerator -- Architected to optimize the performance of the flash with the CPU to provide single cycle random access to the flash up to 80 MHz system clock speed -- Configurable read buffering and line prefetch support -- Four line read buffers (128 bits wide) and a prefetch controller Hardware and software configurable read and write access protections on a per-master basis Interface to the flash array controller is pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs Configurable access timing allowing use in a wide range of system frequencies Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) allowing use for emulation of other memory types Software programmable block program/erase restriction control Erase of selected block(s) Read page size of 128 bits (four words) ECC with single-bit correction, double-bit detection Program page size of 128 bits (four words) to accelerate programming ECC single-bit error corrections are visible to software Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC Embedded hardware program and erase algorithm Erase suspend, program suspend and erase-suspended program Shadow information stored in non-volatile shadow block Independent program/erase of the shadow block
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1.3.10
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SRAM
The MPC5634M SRAM module provides a general-purpose up to 94 KB memory block. The SRAM controller includes these features: Supports read/write accesses mapped to the SRAM memory from any master 32 KB or 24 KB block powered by separate supply for standby operation
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17
Overview
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Byte, halfword, word and doubleword addressable ECC performs single-bit correction, double-bit detection on 32-bit data element
1.3.11
BAM
The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by Freescale and is identical for all MPC5634M MCUs. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are: * * * Booting from internal flash memory Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed) Booting from external memory on calibration bus
The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the MPC5634M hardware accordingly. The BAM provides the following features: * * * * * * * * * * * * Sets up MMU to cover all resources and mapping all physical address to logical addresses with minimum address translation Sets up the MMU to allow user boot code to execute as either Classic PowerPC Book E code (default) or as Freescale VLE code Detection of user boot code Automatic switch to serial boot mode if internal flash is blank or invalid Supports user programmable 64-bit password protection for serial boot mode Supports serial bootloading via FlexCAN bus and eSCI using Freescale protocol Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing Supports serial bootloading of either Classic Power Architecture Book E code (default) or Freescale VLE code Supports booting from calibration bus interface Supports censorship protection for internal flash memory Provides an option to enable the core watchdog timer Provides an option to disable the system watchdog timer
1.3.12
eMIOS
The eMIOS (Enhanced Modular Input Output System) module provides the functionality to generate or measuretime events. The channels on this module provide a range of operating modes including the capability to perform dual input capture or dual output compare as well as PWM output. The eMIOS provides the following features: * * 16 channels For compatibility with other family members selected channels and timebases are implemented: -- Channels 0 to 6, 8 to 15, and 23 -- Timebases A, B and C Channels 1, 3, 5 and 6 support modes: -- General Purpose Input/Output (GPIO) -- Single Action Input Capture (SAIC) -- Single Action Output Compare (SAOC) Channels 2, 4, 11 and 13 support all the modes above plus: -- Output Pulse Width Modulation Buffered (OPWMB) Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus: -- Input Period Measurement (IPM)
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MPC5634M Microcontroller Data Sheet, Rev. 2 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
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-- Input Pulse Width Measurement (IPWM) -- Double Action Output Compare {set flag on both matches} (DAOC) -- Modulus Counter Buffered (MCB) -- Output Pulse Width and Frequency Modulation Buffered (OPWFMB) Channel features: -- 24-bit registers for captured/match values -- 24-bit internal counter -- Global prescaler -- Selectable time base -- Can generate its own time base Three 24-bit wide counter buses -- Counter bus A can be driven by channel 23 -- Counter bus B and C are driven by channels 0 and 8, respectively -- Counter bus A can be shared among all channels. Channels 0 to 6 and 8 to 15 can share counter buses B and C, respectively (channel 7 is not implemented). Shared time bases with the eTPU through the counter buses Synchronization among internal and external time bases Shadow FLAG register State of block can be frozen for debug purposes
1.3.13
eTPU2
The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, eTPU2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the eTPU2. MPC5634M devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard eTPU include: * * * * * * * The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input [TCRCLK]) now have an option to run at full system clock speed or system clock / 2 Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode. Added a new User Programmable Channel Mode: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by CHAN. They can also be requested simultaneously at the same instruction. Channel Flags 0 and 1 can now be tested for branching, besides selecting the entry point Channel digital filters can be bypassed 32 channels, each channel is associated with one input and one output signal -- Enhanced input digital filters on the input pins for improved noise immunity. -- Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned to more than one channel as a given time, so each signal can have any functionality. -- Each channel has an event mechanism which supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19
The eTPU2 includes these distinctive features:
Overview
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-- Input and output signal states visible from the host 2 independent 24-bit time bases for channel synchronization: -- First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by output of second time base prescaler -- Second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time -- Both time bases can be exported to the eMIOS timer module -- Both time bases visible from the host Event-triggered microengine: -- Fixed-length instruction execution in two-system-clock microcycle -- 14 KB of code memory (SCM) -- 3 KB of parameter (data) RAM (SPRAM) -- Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected combinations -- 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution -- Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands Resource sharing features support channel use of common channel registers, memory and microengine time: -- Hardware scheduler works as a "task management" unit, dispatching event service routines by predefined, host-configured priority -- Automatic channel context switch when a "task switch" occurs, i.e., one function thread ends and another begins to service a request from other channel: channel-specific registers, flags and parameter base address are automatically loaded for the next serviced channel -- SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or inter-channel -- Hardware implementation of four semaphores support coherent parameter sharing between both eTPU engines -- Dual-parameter coherency hardware support allows atomic access to two parameters by host Test and development support features: -- Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions -- Software breakpoints -- SCM continuous signature-check built-in self test (MISC - multiple input signature calculator), runs concurrently with eTPU2 normal operation The scheduler priority-passing mechanism can be disabled. A new watchdog mechanism kills threads over a programmable timeout. A new counter allows microengine load information collection for performance analysis. Channels 1 and 2 (besides channel 0) can be selected to control the EAC. Timebase prescalers are now reset when the GTBE input is negated, guaranteeing synchronization with eMIOS in all cases. A new MISC flag indicates when an SCM signature calculation round is completed. This allows measuring of the average MISC scan period in a real application situation. A new channel TCCEA flag allows continuous capture even after TDLA is set, making it fully compatible with TPU behavior.
For MPC5634M, the eTPU2 has been further enhanced with these features: * * * * * * *
MPC5634M Microcontroller Data Sheet, Rev. 2 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
* * *
A new branch condition PRSS tells the pin state at the time when a channel (match or transition) service request occurred. MRLEA/B can now be negated independently by microcode. A new Engine Relative address mode allows a function to access SDM address space common to one engine, but distinct between engines.
1.3.14
eQADC
The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels. The eQADC prioritizes and transfers commands from six command conversion command `queues' to the on-chip ADCs or to the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system memory, which is external to the eQADC. The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics. The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully process the digitized waveform. The eQADC provides the following features: * Dual on-chip ADCs -- 2 x 12-bit ADC resolution -- Programmable resolution for increased conversion speed (12 bit, 10 bit, 8 bit) - 12-bit conversion time - 1 s (1M sample/sec) - 10-bit conversion time - 867 ns (1.2M sample/second) - 8-bit conversion time = 733 ns (1.4M sample/second) -- Up to 10-bit accuracy at 500 KSample/s and 9-bit accuracy at 1 MSample/s -- Differential conversions -- Single-ended signal range from 0 to 5 V -- Variable gain amplifiers on differential inputs (x1, x2, x4) -- Sample times of 2 (default), 8, 64 or 128 ADC clock cycles -- Provides time stamp information when requested -- Parallel interface to eQADC CFIFOs and RFIFOs -- Supports both right-justified unsigned and signed formats for conversion results Up to 341 input channels (accessible by both ADCs) 23 additional internal channels for measuring control and monitoring voltages inside the device
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1.3176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21
Overview
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*
*
-- Including Core voltage, I/O voltage, LVI voltages, etc. An internal bandgap reference to allow absolute voltage measurements 4 pairs of differential analog input channels -- Programmable pull-up/pull-down resistors on each differential input for biasing and sensor diagnostic (200 k, 100 k, 5 k) Silicon die temperature sensor -- provides temperature of silicon as an analog value -- read using an internal ADC analog channel -- may be read with either ADC Decimation Filter -- Programmable decimation factor (2 to 16) -- Selectable IIR or FIR filter -- Up to 4th order IIR or 8th order FIR -- Programmable coefficients -- Saturated or non-saturated modes -- Programmable Rounding (Convergent; Two's Complement; Truncated) -- Pre-fill mode to pre-condition the filter before the sample window opens Full duplex synchronous serial interface to an external device -- Free-running clock for use by an external device -- Supports a 26-bit message length Priority based Queues -- Supports six Queues with fixed priority. When commands of distinct Queues are bound for the same ADC, the higher priority Queue is always served first -- Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a deterministic time after the queue trigger -- Supports software and hardware trigger modes to arm a particular Queue -- Generates interrupt when command coherency is not achieved External hardware triggers -- Supports rising edge, falling edge, high level and low level triggers -- Supports configurable digital filter Supports four external 8-to-1 muxes which can expand the input channels to 56 channels total
1.3.15
DSPI
The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the MPC5634M MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data to an external device that implements the Microsecond Bus protocol. There are two identical DSPI blocks on the MPC5634M MCU. The DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) to improve high speed operation. The DSPIs have three configurations: * * Serial peripheral interface (SPI) configuration where the DSPI operates as an up to 16-bit SPI with support for queues Enhanced deserial serial interface (DSI) configuration where DSPI serializes up to 32 bits with three possible sources per bit -- eTPU, eMIOS, new virtual GPIO registers as possible bit source
MPC5634M Microcontroller Data Sheet, Rev. 2 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
*
-- Programmable inter-frame gap in continuous mode -- Bit source selection allows microsecond bus downlink with command or data frames up to 32 bits -- Microsecond bus dual receiver mode Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI configurations interleaving DSI frames with SPI frames, giving priority to SPI frames
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or through host software. The DSPI supports these SPI features: * * * * * * * * * Full-duplex, synchronous transfers Selectable LVDS Pads working at 40 MHz for SOUT, SIN and SCK pins Master and Slave Mode Buffered transmit operation using the TX FIFO with parameterized depth of 1 to 16 entries Buffered receive operation using the RX FIFO with parameterized depth of 1 to 16 entries TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues Visibility into the TX and RX FIFOs for ease of debugging FIFO Bypass Mode for low-latency updates to SPI queues Programmable transfer attributes on a per-frame basis: -- Parameterized number of transfer attribute registers (from two to eight) -- Serial clock with programmable polarity and phase -- Various programmable delays: - PCS to SCK delay - SCK to PCS delay - Delay between frames -- Programmable serial frame size of 4 to 16 bits, expandable with software control -- Continuously held chip select capability 6 Peripheral Chip Selects, expandable to 64 with external demultiplexer Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer DMA support for adding entries to TX FIFO and removing entries from RX FIFO: -- TX FIFO is not full (TFFF) -- RX FIFO is not empty (RFDF) 6 Interrupt conditions: -- End of queue reached (EOQF) -- TX FIFO is not full (TFFF) -- Transfer of current frame complete (TCF) -- Attempt to transmit with an empty Transmit FIFO (TFUF) -- RX FIFO is not empty (RFDF) -- FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when the TxFIFO is empty) -- FIFO Overrun (serial frame received while RX FIFO is full) Modified transfer formats for communication with slower peripheral devices Continuous Serial Communications Clock (SCK) Power savings via support for Stop Mode Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration, supporting the Microsecond Bus downstream frame format 2 sources of the serialized data:
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23
* * *
*
* * * *
The DSPIs also support these features unique to the DSI and CSI configurations: *
Overview
*
* *
* * *
-- eTPU_A and eMIOS output channels -- Memory-mapped register in the DSPI Destinations for the deserialized data: -- eTPU_A and eMIOS input channels -- SIU External Interrupt Request inputs -- Memory-mapped register in the DSPI Deserialized data is provided as Parallel Output signals and as bits in a memory-mapped register Transfer initiation conditions: -- Continuous -- Edge sensitive hardware trigger -- Change in data Pin serialization/deserialization with interleaved SPI frames for control and diagnostics Continuous serial communications clock Support for parallel and serial chaining of up to four DSPI blocks
1.3.16
eSCI
The enhanced serial communications interface (eSCI) allows asynchronous serial communications with peripheral devices and other MCUs. It includes special support to interface to Local Interconnect Network (LIN) slave devices. The eSCI block provides the following features: * * * * * * * Full-duplex operation Standard mark/space non-return-to-zero (NRZ) format 13-bit baud rate selection Programmable 8-bit or 9-bit, data format Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond bus standard Automatic parity generation LIN support -- Autonomous transmission of entire frames -- Configurable to support all revisions of the LIN standard -- Automatic parity bit generation -- Double stop bit after bit error -- 10- or 13-bit break support Separately enabled transmitter and receiver Programmable transmitter output parity 2 receiver wake up methods: -- Idle line wake-up -- Address mark wake-up Interrupt-driven operation with flags Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection DMA support for both transmit and receive data -- Global error bit stored with receive data in system RAM to allow post processing of errors
* * *
* * * * *
MPC5634M Microcontroller Data Sheet, Rev. 2 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
1.3.17
FlexCAN
The MPC5634M MCU contains two controller area network (FlexCAN) blocks. The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. FlexCAN module `A' contains 64 message buffers (MB); FlexCAN module `C' contains 32 message buffers. The FlexCAN module provides the following features: * * Based on and including all existing features of the Freescale TouCAN module Full Implementation of the CAN protocol specification, Version 2.0B -- Standard data and remote frames -- Extended data and remote frames -- Zero to eight bytes data length -- Programmable bit rate up to 1 Mbit/s Content-related addressing 64 / 32 message buffers of zero to eight bytes data length Individual Rx Mask Register per message buffer Each message buffer configurable as Rx or Tx, all supporting standard and extended messages Includes 1088 / 544 bytes of embedded memory for message buffer storage Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers Full featured Rx FIFO with storage capacity for six frames and internal pointer handling Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability Selectable backwards compatibility with previous FlexCAN versions Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock Listen only mode capability Programmable loop-back mode supporting self-test operation 3 programmable Mask Registers Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority Time Stamp based on 16-bit free-running timer Global network time, synchronized by a specific message Maskable interrupts Warning interrupts when the Rx and Tx Error Counters reach 96 Independent of the transmission medium (an external transceiver is assumed) Multi master concept High immunity to EMI Short latency time due to an arbitration scheme for high-priority messages Low power mode, with programmable wake-up on bus activity
* * * * * * * * * * * * * * * * * * * * * * *
1.3.18
* *
System Timers
The system timers provide two distinct types of system timer: Periodic interrupts/triggers using the Peripheral Interrupt Timer (PIT) Operating system task monitors using the System Timer Module (STM)
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25
Overview
1.3.18.1
Peripheral Interrupt Timer (PIT)
The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has no external input or output pins and is intended to be used to provide system `tick' signals to the operating system, as well as periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is clocked by the crystal clock. This one channel is also referred to as Real Time Interrupt (RTI) and is used to wakeup the device from low power stop mode. The following features are implemented in the PIT: * * * * * * 5 independent timer channels Each channel includes 32-bit wide down counter with automatic reload 4 channels clocked from system clock 1 channel clocked from crystal clock (wake-up timer) Wake-up timer remains active when System STOP mode is entered. Used to restart system clock after predefined time-out period Each channel can optionally generate an interrupt request or a trigger event (to trigger eQADC queues) when the timer reaches zero
1.3.18.2
System Timer Module (STM)
The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR (see http://www.autosar.org). It consists of a single 32-bit counter, clocked by the system clock, and four independent timer comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value. The following features are implemented in the STM: * * * * One 32-bit up counter with 8-bit prescaler Four 32-bit compare channels Independent interrupt source for each channel Counter can be stopped in debug mode
1.3.19
Software Watchdog Timer (SWT)
The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window. The following features are implemented: * * * * * * * 32-bit modulus counter Clocked by system clock or crystal clock Optional programmable watchdog window mode Can optionally cause system reset or interrupt request on timeout Reset by writing a software key to memory mapped register Enabled out of reset Configuration is protected by a software key or a write-once register
1.3.20
Nexus Port Controller
The NPC (Nexus Port Controller) block provides real-time development support capabilities for the MPC5634M Power Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility. The NPC block is an integration of several individual Nexus blocks that are selected to provide the development support interface for the MPC5634M. The NPC block
MPC5634M Microcontroller Data Sheet, Rev. 2 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
interfaces to the host processor (e200z335), eTPU, and internal buses to provide development support as per the IEEE-ISTO 5001-2003 standard. The development support provided includes program trace and run-time access to the MCUs internal memory map and access to the Power Architecture and eTPU internal registers during halt. The Nexus interface also supports a JTAG only mode using only the JTAG pins. MPC5634M in the production 144 LQFP supports a 3.3 V reduced (4-bit wide) Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable I/O count of the device. When using this Nexus port as IO, Nexus trace is still possible using VertiCal calibration. In the VertiCal calibration package, the full 12-bit Auxiliary port is available.
NOTE
In the VertiCal package, the full Nexus Auxiliary port shares balls with the addresses of the calibration bus. Therefore multiplexed address/data bus mode must be used for the calibration bus when using full width Nexus trace in VertiCal assembly. The following features are implemented: * 5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK) -- Always available in production package -- Supports both JTAG Boundary Scan and debug modes -- 3.3 V interface -- Supports Nexus class 1 features -- Supports Nexus class 3 read/write feature 9-pin Reduced Port interface in 144 LQFP production package -- Alternate function as IO -- 5 V (in GPIO or alternate function mode), 3.3 V (in Nexus mode) interface -- Auxiliary Output port - 1 MCKO (message clock out) pin - 4 MDO (message data out) pins - 2 MSEO (message start/end out) pins - 1 EVTO (event out) pin -- Auxiliary input port - 1 EVTI (event in) pin 17-pin Full Port interface in VertiCal calibration package -- 3.3 V interface -- Auxiliary Output port - 1 MCKO (message clock out) pin - 4 or 12 MDO (message data out) pins (8 extra full port pins shared with calibration bus) - 2 MSEO (message start/end out) pins - 1 EVTO (event out) pin -- Auxiliary input port - 1 EVTI (event in) pin Host processor (e200) development support features -- IEEE-ISTO 5001-2003 standard class 2 compliant -- Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced. -- Watchpoint trigger enable of program trace messaging -- Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be halted when the CPU writes a specific value to a memory location - 4 data value breakpoints
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27
*
*
*
Overview
- CPU only - Detects `equal' and `not equal' - Byte, half word, word (naturally aligned)
NOTE
This feature is imprecise due to CPU pipelining. * -- Subset of Power Architecture Book E software debug facilities with OnCE block (Nexus class 1 features) eTPU development support features -- IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU -- Nexus based breakpoint configuration and single step support (JTAG feature of the eTPU) Run-time access to the on-chip memory map via the Nexus read/write access protocol. This feature supports accesses for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid prototyping for powertrain automotive development systems. All features are independently configurable and controllable via the IEEE 1149.1 I/O port Power-on-reset status indication during reset via MDO[0] in disabled and reset modes
*
* *
1.3.21
JTAG
The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 standard and supports the following features: * * * IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO) A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: -- BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP A 5-bit instruction register that supports the additional following public instructions: -- ACCESS_AUX_TAP_NPC -- ACCESS_AUX_TAP_ONCE -- ACCESS_AUX_TAP_eTPU -- ACCESS_CENSOR 3 test data registers to support JTAG Boundary Scan mode -- Bypass register -- Boundary scan register -- Device identification register A TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry Censorship Inhibit Register -- 64-bit Censorship password register -- If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash shadow row, Censorship is disabled until the next system reset
*
* *
1.4
1.4.1
MPC5634M Series Architecture
Block Diagram
Figure 1 shows a top-level block diagram of the MPC5634M series.
MPC5634M Microcontroller Data Sheet, Rev. 2 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Overview
Test Controller
JTAG Port
JTAG
S
Calibration Bus Interface Flash 1.5 MB SRAM 62 KB
Nexus
NMI
M
3 x 4 64-bit Crossbar Switch
Nexus Port
e200z335
SPE
Instructions
S
Data
NMI
eTPU
SIU
critical
MMU
Nexus 2+
S S
Interrupt Requests from Peripheral Blocks & eDMA
eDMA Interrupt Controller (INTC)
M
Clocks
CQM
PLL STM SWT PIT
DMA Requests from Peripheral Blocks
Voltage Regulator (1.2V, 3.3V, STB RAM)
eDMA, FLASH, Bridge B, crossbar, SRAM Configuration
32 KB
M
Vstby
BAM
Peripheral Bridge
Nexus
SIU
Interrupt Request Reset Control External Interrupt Request IMUX GPIO & Pad Control
eTPU
NEXUS 1
16 Ch. eMIOS
2x DSPIs
2x eSCIs
2x CANs
eQADC ADCI
Serial Analog IF
32 Ch.+ Engine RAM 14 KB/3 KB ADC ADC
Analog
AMUX
Decimation Filter
I/O
...
...
...
...
Temp. Sensor
Figure 1. MPC5634M Series Block Diagram
1.4.2
Block Summary
Table 2. MPC5634M Series Block Summary
Block Function Executes programs and interrupt handlers. Provides storage for program code, constants, and variables Provides storage for program code, constants, and variables Transfers data across the crossbar switch to/from peripherals attached to the VertiCal connector
Table 2 summarizes the functions of the blocks present on the MPC5634M series microcontrollers.
E200z3 core Flash memory RAM (random-access memory) Calibration bus
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29
Pinout and Signal Description
Table 2. MPC5634M Series Block Summary (continued)
Block DMA (direct memory access) DSPI (deserial serial peripheral interface) Function Performs complex data movements with minimal intervention from the core Provides a synchronous serial interface for communication with external devices
eMIOS (enhanced modular input-output system) Provides the functionality to generate or measure events eQADC (enhanced queued analog-to-digital converter) eSCI (serial communication interface) eTPU (enhanced time processor unit) FlexCAN (controller area network) FMPLL (frequency-modulated phase-locked loop) INTC (interrupt controller) JTAG controller NPC (Nexus Port Controller) PIT (peripheral interrupt timer) Temperature sensor SWT (Software Watchdog Timer) STM (System Timer Module) Provides accurate and fast conversions for a wide range of applications Allows asynchronous serial communications with peripheral devices and other microcontroller units Processes real-time input events, performs output waveform generation, and accesses shared data without host intervention Supports the standard CAN communications protocol Generates high-speed system clocks and supports the programmable frequency modulation of these clocks Provides priority-based preemptive scheduling of interrupt requests Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard Produces periodic interrupts and triggers Provides the temperature of the device as an analog value Provides protection from runaway code Timer providing a set of output compare events to support AutoSAR and operating system tasks
2
* *
Pinout and Signal Description
Pins labeled "NC" are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable device behavior or damage. Pins labeled "Reserved" are to be tied to ground. Not doing so may cause unpredictable device behavior.
This section contains the pinouts for all production packages for the MPC5634M family of devices. Please note the following:
2.1
100 LQFP Pinout (all 100-pin devices)
Figure 2 shows the pinout for the 100-pin LQFP.
MPC5634M Microcontroller Data Sheet, Rev. 2 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Freescale Semiconductor
AN[11] / ANZ AN[9] / ANX VDDA VSSA AN[10]-AN[39]-ANY AN[8]-AN[38]-ANW VDDREG VRCCTL VSTBY VRC33 eTPU_A[31] / PCS_C[4] / eTPU_A[13] / GPIO[145] eTPU_A[30] / PCS_C[3] / eTPU_A[11] / GPIO[144] eTPU_A[29] / PCS_C[2] / GPIO[143] GPIO[141] / eTPU_A[28] / PCS_C[1] / GPIO[142] eTPU_A[27] / IRQ[15] / SOUT_C_LVDS- / SOUTB eTPU_A[26] / IRQ[14] / SOUT_C_LVDS+ / GPIO[140] eTPU_A[25] / IRQ[13] / SCK_C_LVDS- / GPIO[139] eTPU_A[24] / IRQ[12] / SCK_C_LVDS+ / GPIO[138] VSS VDDEH1A VDD eTPU_A[15] / PCS_B[5] / GPIO[129] VDDEH1B eTPU_A[14] / PCS_B[4] / eTPU_A[9] / GPIO[128] VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100-Pin LQFP
MPC5634M Microcontroller Data Sheet, Rev. 2
eTPU_A[13] / PCS_B[3] / GPIO[127] eTPU_A[8] / eTPU_A[20] / SOUT_B_LVDS- / GPIO[122] eTPU_A[7] / eTPU_A[19] / SOUT_B_LVDS+ / eTPU_A[6] / GPIO[121] eTPU_A[6] / eTPU_A[18] / SCK_B_LVDS- / GPIO[120] eTPU_A[5] / eTPU_A[17] / SCK_B_LVDS+ / GPIO[119] VDDEH4A eTPU_A[4] / eTPU_A[16] / GPIO[118] VSS eTPU_A[3] / eTPU_A[15] / GPIO[117] eTPU_A[2] / eTPU_A[14] / GPIO[116] eTPU_A[1] / eTPU_A[13] / GPIO[115] eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114] VDD eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179 eMIOS[8] / eTPU_A[8] / TXDB / GPIO[187] eMIOS[9] / eTPU_A[9] / RXDB / GPIO[188] VSS VDDEH4B eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191] eMIOS[14] / IRQ[0] / eTPU_A[29] / GPIO[193] CNTX_A / TXD_A / GPIO[83] CNRX_A / RXD_A / GPIO[84] PLLREF / IRQ[4]/ETRIG[0] / GPIO[208] BOOTCFG1 / IRQ[3] / ETRIG[1] / GPIO[212] WKPCFG / NMI / GPIO[213]
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Figure 2. 100-pin LQFP Pinout (top view; all 100-pin devices)
Preliminary--Subject to Change Without Notice
TMS TDI / eMIOS[5] / GPIO[232] TCK VSS VDDEH7 TDO / eMIOS[6] / GPIO[228] JCOMP PCS_B[3] / SIN_C / GPIO[108] SIN_B / PCS_C[2] / GPIO[103] VDDEH6B VSS SCK_B / PCS_C[1] / GPIO[102] PCS_B[4] / SCK_C / GPIO[109] VDD RSTOUT CNTX_C / GPIO[87] CNRX_C / GPIO[88] RESET VSS VDDEH6A VSSPLL XTAL EXTAL / EXTCLK VDDPLL VSS
AN[21] AN[0] (DAN0+) AN[1] (DAN0-) AN[2] (DAN1+) AN[3] (DAN1-) AN[4] (DAN2+) AN[5] (DAN2-) AN[6] (DAN3+) AN[7] (DAN3-) REFBYPC VRH VRL AN[23] AN[25] AN[28] AN[31] AN[33] AN[35] VDD ETPU_A[19] / AN[12] / MA[0] / SDS_B ETPU_A[21] / AN[13] / MA[1] / SDO ETPU_A[27] / AN[14] / MA[2] / SDI ETPU_A[29] / AN[15] / FCK VSS VDDEH7
Pinout and Signal Description
31
Pinout and Signal Description
2.2
144 LQFP Pinout (all 144-pin devices)
AN[21] AN[0] (DAN0+) AN[1] (DAN0-) AN[2] (DAN1+) AN[3] (DAN1-) AN[4] (DAN2+) AN[5] (DAN2-) AN[6] (DAN3+) AN[7] (DAN3-) REFBYPC VRH VRL AN[22] AN[23] AN[24] AN[25] AN[27] AN[28] AN[30] AN[31] AN[32] AN[33] AN[34] AN[35] VDD ETPU_A[19] / AN[12] / MA[0] / SDS_B ETPU_A[21] / AN[13] / MA[1] / SDO ETPU_A[27] / AN[14] / MA[2] / SDI ETPU_A[29] / AN[15] / FCK VSS MDO[3] / eTPU_A[25] / GPIO[223] VDDEH7 MDO[2] / eTPU_A[21] / GPIO[222] MDO[1] / eTPU_A[19] / GPIO[221]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
AN[18] AN[17] AN[16] AN[11] / ANZ AN[9] / ANX VDDA VSSA AN[10]-AN[39]-ANY AN[8]-AN[38]-ANW VDDREG VRCCTL VSTBY VRC33 eTPU_A[31] / PCS_C[4] / eTPU_A[13] / GPIO[145] eTPU_A[30] / PCS_C[3] / eTPU_A[11] / GPIO[144] eTPU_A[29] / PCS_C[2] / GPIO[143] GPIO[141] / eTPU_A[28] / PCS_C[1] / GPIO[142] eTPU_A[27] / IRQ[15] / SOUT_C_LVDS- / SOUTB eTPU_A[26] / IRQ[14] / SOUT_C_LVDS+ / GPIO[140] eTPU_A[25] / IRQ[13] / SCK_C_LVDS- / GPIO[139] eTPU_A[24] / IRQ[12] / SCK_C_LVDS+ / GPIO[138] VSS VDDEH1A eTPU_A[22] / IRQ[10] / eTPU_A[17] / GPIO[136] VDD eTPU_A[21] / IRQ[9] / GPIO[135] eTPU_A[20] / IRQ[8] / GPIO[134] eTPU_A[19] / GPIO[133] eTPU_A[18] / GPIO[132] eTPU_A[17] / GPIO[131] eTPU_A[16] / GPIO[130] eTPU_A[15] / PCS_B[5] / GPIO[129] VDDEH1B eTPU_A[14] / PCS_B[4] / eTPU_A[9] / GPIO[128] VSS
eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137]
MDO[0] / eTPU_A[13] / GPIO[220] MSEO[0] / eTPU_A[27] / GPIO[224]
144-Pin LQFP
Figure 3 shows the pinout for the 144-pin LQFP. Figure 3. 144-pin LQFP Pinout (top view; all 144-pin devices)
MPC5634M Microcontroller Data Sheet, Rev. 2 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor
eTPU_A[13] / PCS_B[3] / GPIO[127 eTPU_A[12] / PCS_B[1] / GPIO[126] eTPU_A[11] / eTPU_A[23] / GPIO[125] eTPU_A[10] / eTPU_A[22] / GPIO[124] eTPU_A[9] / eTPU_A[21] / GPIO[123] eTPU_A[8] / eTPU_A[20] / SOUT_B_LVDS- / GPIO[122] eTPU_A[7] / eTPU_A[19] / SOUT_B_LVDS+ / eTPU_A[6] / GPIO[121] eTPU_A[6] / eTPU_A[18] / SCK_B_LVDS- / GPIO[120] eTPU_A[5] / eTPU_A[17] / SCK_B_LVDS+ / GPIO[119] VDDEH4A eTPU_A[4] / eTPU_A[16] / GPIO[118] VSS eTPU_A[3] / eTPU_A[15] / GPIO[117] eTPU_A[2] / eTPU_A[14] / GPIO[116] eTPU_A[1] / eTPU_A[13] / GPIO[115] eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114] VDD eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179 eMIOS[2] / eTPU_A[2] / GPIO[181] eMIOS[4] / eTPU_A[4] / GPIO[183] eMIOS[8] / eTPU_A[8] / TXDB / GPIO[187] eMIOS[9] / eTPU_A[9] / RXDB / GPIO[188] VSS eMIOS[10] / GPIO[189] VDDEH4B eMIOS[11] / GPIO[190] eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191] eMIOS[14] / IRQ[0] / eTPU_A[29] / GPIO[193] eMIOS[23] / GPIO[202] CNTX_A / TXD_A / GPIO[83] CNRX_A / RXD_A / GPIO[84] PLLREF / IRQ[4]/ETRIG[0] / GPIO[208] RXD_B / GPIO[92] BOOTCFG1 / IRQ[3] / ETRIG[1] / GPIO[212] WKPCFG / NMI / GPIO[213] TXD_B / GPIO[91]
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TMS TDI / eMIOS[5] / GPIO[232] EVTO / eTPU_A[4] / GPIO[227] TCK VSS EVTI / eTPU_A[2] / GPIO[231] VDDEH7 MSEO[1] / eTPU_A[29] / GPIO[225] TDO / eMIOS[6] / GPIO[228] MCKO / CLKOUT / OSCCLK / GPIO[219] JCOMP PCS_B[3] / SIN_C / GPIO[108] SOUT_B / PCS_C[5] / GPIO[104] SIN_B / PCS_C[2] / GPIO[103] PCS_B[0] / GPIO[105] VDDEH6B PCS_B[1] / GPIO[106] VSS PCS_B[2] / SOUT_C / GPIO[107] SCK_B / PCS_C[1] / GPIO[102] PCS_B[4] / SCK_C / GPIO[109]
PCS_B[5] / PCS_C[0] / GPIO[110]
VDD RSTOUT CNTX_C / GPIO[87] TXD_A / eMIOS[13] / GPIO[89] RXD_A / eMIOS[15] / GPIO[90] CNRX_C / GPIO[88] RESET VSS VDDEH6A VSSPLL XTAL EXTAL / EXTCLK VDDPLL VSS
Pinout and Signal Description
2.3
176 LQFP Pinout (MPC5634M)
NC AN[37] AN[36] AN[21] AN[0] (DAN0+) AN[1] (DAN0-) AN[2] (DAN1+) AN[3] (DAN1-) AN[4] (DAN2+) AN[5] (DAN2-) AN[6] (DAN3+) AN[7] (DAN3-) REFBYPC VRH VRL AN[22] AN[23] AN[24] AN[25] AN[27] AN[28] AN[30] AN[31] AN[32] AN[33] AN[34] AN[35] VDD ETPU_A[19] / AN[12] / MA[0] / SDS_B ETPU_A[21] / AN[13] / MA[1] / SDO ETPU_A[27] / AN[14] / MA[2] / SDI ETPU_A[29] / AN[15] / FCK GPIO[207] GPIO[206] GPIO[99] GPIO[98] VSS eTPU_A[25]_O VDDEH7 eTPU_A[21]_O eTPU_A[19]_O eTPU_A[13]_O eTPU_A[27]_O VSS AN[18] AN[17] AN[16] AN[11] / ANZ AN[9] / ANX VDDA VSSA AN[10]-AN[39]-ANY AN[8]-AN[38]-ANW VDDREG VRCCTL VSTBY VRC33 MCKO / CLKOUT / OSCCLK / GPIO[219] VSS VDDE12 MDO[0] / eTPU_A[13] / GPIO[220] MDO[1] / eTPU_A[19] / GPIO[221] MDO[2] / eTPU_A[21] / GPIO[222] MDO[3] / eTPU_A[25] / GPIO[223] eTPU_A[31]/PCS_C[4]/eTPU_A[13]/GPIO[145] eTPU_A[30]/PCS_C[3]/eTPU_A[11]/GPIO[144] eTPU_A[29]/PCS_C[2]/GPIO[143] GPIO[141]/eTPU_A[28]/PCS_C[1]/GPIO[142] eTPU_A[27]/IRQ[15]/SOUT_C_LVDS-/SOUTB eTPU_A[26]/IRQ[14]/SOUT_C_LVDS+/GPIO[140] eTPU_A[25]/IRQ[13]/SCK_C_LVDS-/GPIO[139] eTPU_A[24]/IRQ[12]/SCK_C_LVDS+/GPIO[138] VSS VDDEH1A eTPU_A[22]/IRQ[10]/eTPU_A[17]/GPIO[136] VDD eTPU_A[21] / IRQ[9] / GPIO[135] eTPU_A[20] / IRQ[8] / GPIO[134] eTPU_A[19] / GPIO[133] eTPU_A[18] / GPIO[132] eTPU_A[17] / GPIO[131] eTPU_A[16] / GPIO[130] eTPU_A[15] / PCS_B[5] / GPIO[129] VDDEH1B eTPU_A[14]/PCS_B[4]/eTPU_A[9]/GPIO[128] VSS NC
eTPU_A[23]/IRQ[11]/eTPU_A[21]/GPIO[137]
Figure 4 shows the 176-pin LQFP pinout for the for the MPC5634M (1536 KB flash memory).
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
176-Pin LQFP
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
NC TMS TDI / eMIOS[5] / GPIO[232] eTPU_A[4]_O TCK VSS eTPU_A[2]_O VDDEH7
eTPU_A[29]_O
TDO / eMIOS[6] / GPIO[228] GPIO[219] JCOMP EVTO / eTPU_A[4] / GPIO[227] VDDE12
MSEO[0] / eTPU_A[27] / GPIO[224]
MSEO[1] / eTPU_A[29] / GPIO[225] EVTI / eTPU_A[2] / GPIO[231] VSS PCS_B[3] / SIN_C / GPIO[108] SOUT_B / PCS_C[5] / GPIO[104] SIN_B / PCS_C[2] / GPIO[103] PCS_B[0] / GPIO[105] VDDEH6B PCS_B[1] / GPIO[106] VSS PCS_B[2] / SOUT_C / GPIO[107] SCK_B / PCS_C[1] / GPIO[102] PCS_B[4] / SCK_C / GPIO[109]
PCS_B[5] / PCS_C[0] / GPIO[110]
VDD RSTOUT CNTX_C / GPIO[87] TXD_A / eMIOS[13] / GPIO[89] RXD_A / eMIOS[15] / GPIO[90] CNRX_C / GPIO[88] RESET VSS VDDEH6A VSSPLL XTAL EXTAL / EXTCLK VDDPLL VSS NC
Figure 4. 176-pin LQFP Pinout (MPC5634M; top view)
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33
NC eTPU_A[13] / PCS_B[3] / GPIO[127] eTPU_A[12] / PCS_B[1] / GPIO[126] eTPU_A[11] / eTPU_A[23] / GPIO[125] eTPU_A[10] / eTPU_A[22] / GPIO[124] eTPU_A[9] / eTPU_A[21] / GPIO[123] eTPU_A[8] / eTPU_A[20] / SOUT_B_LVDS- / GPIO[122] eTPU_A[7] / eTPU_A[19] / SOUT_B_LVDS+ / eTPU_A[6] / GPIO[121] eTPU_A[6] / eTPU_A[18] / SCK_B_LVDS- / GPIO[120] eTPU_A[5] / eTPU_A[17] / SCK_B_LVDS+ / GPIO[119] VDDEH4A eTPU_A[4] / eTPU_A[16] / GPIO[118] VSS eTPU_A[3] / eTPU_A[15] / GPIO[117] eTPU_A[2] / eTPU_A[14] / GPIO[116] eTPU_A[1] / eTPU_A[13] / GPIO[115] eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114] VDD eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
eMIOS[2] / eTPU_A[2] / GPIO[181] NC eMIOS[4] / eTPU_A[4] / GPIO[183] NC NC eMIOS[8] / eTPU_A[8] / TXDB / GPIO[187] eMIOS[9] / eTPU_A[9] / RXDB / GPIO[188] VSS eMIOS[10] / GPIO[189] VDDEH4B eMIOS[11] / GPIO[190] eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
eMIOS[23] / GPIO[202] CNTX_A / TXD_A / GPIO[83] CNRX_A / RXD_A / GPIO[84 PLLREF / IRQ[4]/ETRIG[0] / GPIO[208] RXD_B / GPIO[92] BOOTCFG1 / IRQ[3] / ETRIG[1] / GPIO[212] WKPCFG / NMI / GPIO[213] TXD_B / GPIO[91] NC
eMIOS[13] / GPIO[192] eMIOS[14] / IRQ[0] / eTPU_A[29] / GPIO[193] eMIOS[15] / IRQ[1] / GPIO[194]
eMIOS[1] / eTPU_A[1] / GPIO[180]
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Pinout and Signal Description
2.4
176 LQFP Pinout (MPC5633M)
NC NC NC AN[21] AN[0] (DAN0+) AN[1] (DAN0-) AN[2] (DAN1+) AN[3] (DAN1-) AN[4] (DAN2+) AN[5] (DAN2-) AN[6] (DAN3+) AN[7] (DAN3-) REFBYPC VRH VRL AN[22] AN[23] AN[24] AN[25] AN[27] AN[28] AN[30] AN[31] AN[32] AN[33] AN[34] AN[35] VDD ETPU_A[19] / AN[12] / MA[0] / SDS_B ETPU_A[21] / AN[13] / MA[1] / SDO ETPU_A[27] / AN[14] / MA[2] / SDI ETPU_A[29] / AN[15] / FCK NC NC NC NC VSS eTPU_A[25]_O VDDEH7 eTPU_A[21]_O eTPU_A[19]_O eTPU_A[13]_O eTPU_A[27]_O RESERVED AN[18] AN[17] AN[16] AN[11] / ANZ AN[9] / ANX VDDA VSSA AN[10]-AN[39]-ANY AN[8]-AN[38]-ANW VDDREG VRCCTL VSTBY VRC33 MCKO / CLKOUT / OSCCLK / GPIO[219] RESERVED RESERVED MDO[0] / eTPU_A[13] / GPIO[220] MDO[1] / eTPU_A[19] / GPIO[221] MDO[2] / eTPU_A[21] / GPIO[222] MDO[3] / eTPU_A[25] / GPIO[223] eTPU_A[31]/PCS_C[4]/eTPU_A[13]/GPIO[145] eTPU_A[30]/PCS_C[3]/eTPU_A[11]/GPIO[144] eTPU_A[29]/PCS_C[2]/GPIO[143] GPIO[141]/eTPU_A[28]/PCS_C[1]/GPIO[142] eTPU_A[27]/IRQ[15]/SOUT_C_LVDS-/SOUTB eTPU_A[26]/IRQ[14]/SOUT_C_LVDS+/GPIO[140] eTPU_A[25]/IRQ[13]/SCK_C_LVDS-/GPIO[139] eTPU_A[24]/IRQ[12]/SCK_C_LVDS+/GPIO[138] VSS VDDEH1A eTPU_A[22]/IRQ[10]/eTPU_A[17]/GPIO[136] VDD eTPU_A[21] / IRQ[9] / GPIO[135] eTPU_A[20] / IRQ[8] / GPIO[134] eTPU_A[19] / GPIO[133] eTPU_A[18] / GPIO[132] eTPU_A[17] / GPIO[131] eTPU_A[16] / GPIO[130] eTPU_A[15] / PCS_B[5] / GPIO[129] VDDEH1B eTPU_A[14]/PCS_B[4]/eTPU_A[9]/GPIO[128] VSS NC
eTPU_A[23]/IRQ[11]/eTPU_A[21]/GPIO[137]
Figure 5 shows the pinout for the 176-pin LQFP for the MPC5633M (1024 KB flash memory).
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
176-Pin LQFP
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
NC TMS TDI / eMIOS[5] / GPIO[232] eTPU_A[4]_O TCK VSS eTPU_A[2]_O VDDEH7
eTPU_A[29]_O
TDO / eMIOS[6] / GPIO[228] GPIO[219] JCOMP EVTO / eTPU_A[4] / GPIO[227] RESERVED
MSEO[0] / eTPU_A[27] / GPIO[224]
MSEO[1] / eTPU_A[29] / GPIO[225] EVTI / eTPU_A[2] / GPIO[231] RESERVED PCS_B[3] / SIN_C / GPIO[108] SOUT_B / PCS_C[5] / GPIO[104] SIN_B / PCS_C[2] / GPIO[103] PCS_B[0] / GPIO[105] VDDEH6B PCS_B[1] / GPIO[106] VSS PCS_B[2] / SOUT_C / GPIO[107] SCK_B / PCS_C[1] / GPIO[102] PCS_B[4] / SCK_C / GPIO[109]
PCS_B[5] / PCS_C[0] / GPIO[110]
VDD RSTOUT CNTX_C / GPIO[87] TXD_A / GPIO[89] RXD_A / GPIO[90] CNRX_C / GPIO[88] RESET VSS VDDEH6A VSSPLL XTAL EXTAL / EXTCLK VDDPLL VSS NC
NC
NC eTPU_A[13] / PCS_B[3] / GPIO[127] eTPU_A[12] / PCS_B[1] / GPIO[126] eTPU_A[11] / eTPU_A[23] / GPIO[125] eTPU_A[10] / eTPU_A[22] / GPIO[124] eTPU_A[9] / eTPU_A[21] / GPIO[123] eTPU_A[8] / eTPU_A[20] / SOUT_B_LVDS- / GPIO[122] eTPU_A[7] / eTPU_A[19] / SOUT_B_LVDS+ / eTPU_A[6] / GPIO[121] eTPU_A[6] / eTPU_A[18] / SCK_B_LVDS- / GPIO[120] eTPU_A[5] / eTPU_A[17] / SCK_B_LVDS+ / GPIO[119] VDDEH4A eTPU_A[4] / eTPU_A[16] / GPIO[118] VSS eTPU_A[3] / eTPU_A[15] / GPIO[117] eTPU_A[2] / eTPU_A[14] / GPIO[116] eTPU_A[1] / eTPU_A[13] / GPIO[115] eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114] VDD eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
eMIOS[2] / eTPU_A[2] / GPIO[181] NC eMIOS[4] / eTPU_A[4] / GPIO[183] NC NC eMIOS[8] / eTPU_A[8] / TXDB / GPIO[187] eMIOS[9] / eTPU_A[9] / RXDB / GPIO[188] VSS eMIOS[10] / GPIO[189] VDDEH4B eMIOS[11] / GPIO[190] eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
Figure 5. 176-pin LQFP Pinout (MPC5633M; top view)
MPC5634M Microcontroller Data Sheet, Rev. 2 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor
eMIOS[23] / GPIO[202] CNTX_A / TXD_A / GPIO[83] CNRX_A / RXD_A / GPIO[84 PLLREF / IRQ[4]/ETRIG[0] / GPIO[208] RXD_B / GPIO[92] BOOTCFG1 / IRQ[3] / ETRIG[1] / GPIO[212] WKPCFG / NMI / GPIO[213] TXD_B / GPIO[91] NC
NC eMIOS[14] / IRQ[0] / eTPU_A[29] / GPIO[193] NC
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
2.5
1 VSS
MAPBGA208 Ballmap (MPC5634M)
2 AN9 3 AN11 4 VDDA1 5 VSSA1 6 AN1 7 AN5 8 VRH 9 VRL 10 AN27 11 VSSA0 12 AN12-SDS _B VDD VSS VDD AN39 ETPUA31 ETPUA29 ETPUA27 ETPUA22 ETPUA19 ETPUA15 ETPUA11 ETPUA9 ETPUA4 ETPUA2 VSS VDD AN38 VSS VDD AN37 ETPUA26 ETPUA25 ETPUA17 ETPUA14 ETPUA7 ETPUA6 ETPUA1 ETPUA0 VSS VDD NC AN21 AN17 VSS VDD AN36 ETPUA21 ETPUA18 ETPUA13 VDDEH1 ETPUA0 ETPUA5 VSS VDD GPIO206 EMIOS0 VDD GPIO207 EMIOS4 EMIOS1 VRC33 VDDE7 NC GPIO219 EMIOS2 NC EMIOS9 eTPUA25 EMIOS10 EMIOS8 EMIOS11 VDDEH4 EMIOS12 eTPUA19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AN0 AN34 AN18 AN4 AN16 AN2 REFBYPC AN3 AN6 AN22 AN7 AN24 AN25 AN23 AN30 AN28 AN32 AN31 VDDA0 AN33 AN35 AN13-SDO MDO3 MDO1 VSS TMS TDI TDO PCSB3 PCSB4 TXDA RXDA CNRXC PLLREF VRCCTL VSS VDD CLKOUT VSS MSEO0 EVTO EVTI MCKO SINB PCSB2 GPIO98 RSTOUT WKPCFG VDD TCK NC MSEO1 JCOMP PCSB0 PCSB1 SCKB VDDREG RESET 13 MDO2 14 MDO0 15 VRC33 16 VSS
Freescale Semiconductor Preliminary--Subject to Change Without Notice 35 Monaco 1.5M Data Sheet, Rev. 2
Figure 6 shows the 208-pin MAPBGA ballmap for the MPC5634M (1536 KB flash memory) as viewed from above.
A
B C D E F G H J K L M N P R T
VSTBY VRC33 ETPUA30 ETPUA28 ETPUA24 ETPUA23 ETPUA20 ETPUA16 ETPUA12 ETPUA10 ETPUA8 ETPUA3 NC VSS
AN14-SDI AN15-FCK VDDEH7 VSS VDDE7 VDDEH6 SOUTB GPIO99 PCSB5 CNTXC TXDB RXDB
BOOTCFG1 VSSPLL NC NC VSS VDD EXTAL XTAL VDDPLL VSS
1 1
VRC33 CNTXA CNRXA NC
VSS VDD NC VDDE5
1 eTPUA29
1 eTPUA2
eTPUA21
EMIOS14 eTPUA27 EMIOS15
1 EMIOS23
eTPUA13
Pinout and Signal Description
1 EMIOS13
1 eTPUA4
1
1
eTPU output only channel.
Figure 6. 208-pin MAPBGA Ballmap (MPC5634M; top view)
2.6
1 VSS
MAPBGA208 Ballmap (MPC5633M only)
2 AN9 3 AN11 4 VDDA1 5 VSSA1 6 AN1 7 AN5 8 VRH 9 VRL 10 AN27 11 VSSA0 12 AN12-SDS _B VDD VSS VDD AN39 ETPUA31 ETPUA29 ETPUA27 ETPUA22 ETPUA19 ETPUA15 ETPUA11 ETPUA9 ETPUA4 ETPUA2 VSS VDD AN38 VSS VDD NC ETPUA26 ETPUA25 ETPUA17 ETPUA14 ETPUA7 ETPUA6 ETPUA1 ETPUA0 VSS VDD NC AN21 AN17 VSS VDD NC ETPUA21 ETPUA18 ETPUA13 VDDEH1 ETPUA0 ETPUA5 VSS VDD NC EMIOS0 VDD NC EMIOS4 NC VRC33 VDDE7 NC GPIO219 EMIOS2 NC EMIOS9 eTPUA25 EMIOS10 EMIOS8 EMIOS11 NC VDDEH4 EMIOS12 eTPUA19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AN0 AN34 AN18 AN4 AN16 AN2 REFBYPC AN3 AN6 AN22 AN7 AN24 AN25 AN23 AN30 AN28 AN32 AN31 VDDA0 AN33 AN35 AN13-SDO MDO3 MDO1 VSS TMS TDI TDO PCSB3 PCSB4 TXDA RXDA CNRXC PLLREF VRCCTL VSS VDD CLKOUT VSS MSEO0 EVTO EVTI MCKO SINB PCSB2 NC RSTOUT WKPCFG VDD TCK NC MSEO1 JCOMP PCSB0 PCSB1 SCKB VDDREG RESET 13 MDO2 14 MDO0 15 VRC33 16 VSS
Pinout and Signal Description
36 Preliminary--Subject to Change Without Notice Freescale Semiconductor Monaco 1.5M Data Sheet, Rev. 2
Figure 7 shows the 208-pin MAPBGA ballmap for the MPC5633M (1024 KB flash memory) as viewed from above.
A
B C D E F G H J K L M N P R T
VSTBY VRC33 ETPUA30 ETPUA28 ETPUA24 ETPUA23 ETPUA20 ETPUA16 ETPUA12 ETPUA10 ETPUA8 ETPUA3 NC VSS
AN14-SDI AN15-FCK VDDEH7 VSS VDDE7 VDDEH6 SOUTB NC PCSB5 CNTXC TXDB RXDB
BOOTCFG1 VSSPLL NC NC VSS VDD EXTAL XTAL VDDPLL VSS
1 1
VRC33 CNTXA CNRXA NC
VSS VDD NC VDDE5
1 eTPUA29
1 eTPUA2
eTPUA21
EMIOS14 eTPUA27 NC
1 EMIOS23
eTPUA13
1
1 eTPUA4
1
1
eTPU output only channel.
Figure 7. 208-pin MAPBGA Ballmap (MPC5633M; top view)
2.7
t
Signal Summary
Table 3. MPC563xM Signal Properties
Pad Config. Register (PCR)2 PCR PA Field3 I/O Type Reset State5 Function / State After Reset6 Pin No. 100 144 176 208 MAP LQFP LQFP LQFP BGA
Freescale Semiconductor Preliminary--Subject to Change Without Notice 37 Monaco 1.5M Data Sheet, Rev. 2
Name
Function1
Voltage4
Dedicated GPIO GPIO[98] GPIO[99] GPIO[206] GPIO[207] GPIO[219] GPIO GPIO GPIO GPIO GPIO PCR[98] PCR[99] PCR[206] PCR[207] PCR[219] -- -- -- -- -- I/O I/O I/O I/O I/O VDDEH7 VDDEH7 VDDEH7 VDDEH7 VDDEH7 -/-/-/-/-/GPIO[98] GPIO[99] GPIO[206] GPIO[207] GPIO[219] -- -- -- -- -- -- -- -- -- -- 1417 1427 1437 1447 1227 J158 H138 R48 P58 T6
Reset / Configuration RESET RSTOUT PLLREF IRQ[4] ETRIG[0] GPIO[208] BOOTCFG1 IRQ[3] ETRIG[1] GPIO[212] WKPCFG NMI GPIO[213] External Reset Input External Reset Output FMPLL Mode Selection External Interrupt Request eQADC Trigger Input GPIO Boot Config. Input External Interrupt Request eQADC Trigger Input GPIO Weak Pull Config. Input Non-Maskable Interrupt GPIO -- -- PCR[208] -- -- 011 010 100 000 011 010 100 000 11 10 00 I O I I I I/O I I I I/O I I I/O VDDEH6a VDDEH6a VDDEH6a I / Up RSTOUT/ Low PLLREF / Up RESET / Up RSTOUT/ High - / Up 58 61 48 80 85 68 97 102 83 L16 K15 M14
PCR[212]
VDDEH6a
BOOTCFG / Down
- / Down
49
70
85
M15
PCR[213]
VDDEH6a
WKPCFG / Up
- / Up
50
71
86
L15
Pinout and Signal Description
Calibration9 CAL_ADDR[12:15] CAL_ADDR[16:19] MDO[0:3]10 CAL_ADDR[20:27] MDO[4:11] Calibration Address Bus Calibration Address Bus Nexus Msg Data Out Calibration Address Bus Nexus Msg Data Out PCR[340] PCR[345] -- -- O O O O O VDDE12 VDDE1211 VDDE712 VDDE12 O / Low O / Low13 CAL_ADDR / Low MDO / CAL_ADDR10 / Low MDO / CAL_ADDR14 / Low -- -- -- -- -- -- -- --
PCR[345]
--
O / Low
--
--
--
--
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 PCR[345] PCR[345] -- -- -- -- PCR[338] PCR[339] -- -- -- -- -- -- -- -- -- PCR PA Field3 -- -- -- -- -- -- 11 10 11 10 I/O Type O O O I O O I O O O O O I/O I/O O O O O O Reset State5 O / High15 --16 O / Low O / Low I / Down O / High O / High O / High - / Up - / Up O / High O / High O / High O / High Function / State After Reset6 MSEO14 / CAL_ADDR15 EVTI / CAL_ADDR17 EVTO / High MCKO / Enabled NEXUSCFG / Down CAL_CS / High CAL_CS / High CAL_CS / High - / Up - / Up CAL_OE / High CAL_RD_WR /High CAL_TS / High CAL_WE / High Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Pinout and Signal Description
38 Name Function1 CAL_ADDR[28:29]f: Calibration Address Bus 1]10 Nexus Msg Start/End Out CAL_ADDR[30] EVTI10 CAL_EVTO CAL_MCKO NEXUSCFG Monaco 1.5M Data Sheet, Rev. 2 CAL_CS[0] CAL_CS[2] CAL_ADDR[10] CAL_CS[3] CAL_ADDR[11] CAL_DATA[0:9] CAL_DATA[10:15] CAL_OE CAL_RD_WR CAL_TS ALE CAL_WE_BE [0:1] Freescale Semiconductor Preliminary--Subject to Change Without Notice Calibration Address Bus Nexus Event In Nexus Event Out Nexus Msg Clock Out Nexus/Calibration bus selector Calibration Chip Selects Calibration Chip Selects Calibration Address Bus Calibration Chip Selects Calibration Address Bus Calibration Data Bus Calibration Data Bus Calibration Output Enable Calibration Read/Write Calibration Transfer Start Address Latch Enable Calibration Write Enable Byte Enable EVTI eTPU_A[2] GPIO[231] EVTO eTPU_A[4] GPIO[227] Nexus Event In eTPU A Channel GPIO Nexus Event Out eTPU A Channel GPIO
Voltage
4
VDDE1211 VDDE712 VDDE1211 VDDE712 VDDE1211 VDDE712 VDDE1211 VDDE712 VDDE12 VDDE12 VDDE12 VDDE12 VDDE12 VDDE12 VDDE12 VDDE12 VDDE12 VDDE12
NEXUS PCR[231] 01 10 00 0118 10 00 I O I/O O O I/O VDDEH7 -/-/-- 103 116 E15
PCR[227]
VDDEH7
I / Up
I / Up
--
106
120
D15
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 PCR[219] PCR[220] PCR PA Field3 N/A18 00 01 10 00 0118 10 00 0118 10 00 0118 10 00 0118 10 00 0118 10 00 I/O Type O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O Reset State5 -/-/Function / State After Reset6 -/-/Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA -- -- 99 110 14 17 F15 A14
Freescale Semiconductor Preliminary--Subject to Change Without Notice 39 Monaco 1.5M Data Sheet, Rev. 2
Name
Function1
Voltage
4
MCKO GPIO[219] MDO[0]19 eTPU_A[13] GPIO[220] MDO[1] eTPU_A[19] GPIO[221] MDO[2] eTPU_A[21] GPIO[222] MDO[3] eTPU_A[25] GPIO[223] MSEO[0] eTPU_A[27] GPIO[224] MSEO[1] eTPU_A[29] GPIO[225]
Nexus Msg Clock Out GPIO Nexus Msg Data Out eTPU A Channel GPIO Nexus Msg Data Out eTPU A Channel GPIO Nexus Msg Data Out eTPU A Channel GPIO Nexus Msg Data Out eTPU A Channel GPIO Nexus Msg Start/End Out eTPU A Channel GPIO Nexus Msg Start/End Out eTPU A Channel GPIO
VDDEH7 VDDEH7
PCR[221]
VDDEH7
-/-
-/-
--
111
18
B14
PCR[222]
VDDEH7
-/-
-/-
--
112
19
A13
PCR[223]
VDDEH7
-/-
-/-
--
114
20
B13
PCR[224]
VDDEH7
-/-
-/-
--
109
118
C15
PCR[225]
VDDEH7
-/-
-/-
--
101
117
E16
JTAG / TEST TCK TDI20 eMIOS[5] GPIO[232] TDO20 eMIOS[6] GPIO[228] TMS JCOMP JTAG Test Clock Input JTAG Test Data Input eMIOS Channel GPIO JTAG Test Data Output eMIOS Channel GPIO JTAG Test Mode Select Input JTAG TAP Controller Enable -- PCR[232] -- 0121 10 00 0121 10 00 -- -- I I O I/O O O I/O I I CAN VDDEH7 VDDEH7 TCK / Down -/TCK / Down -/73 74 105 107 128 130 C16 E14
Pinout and Signal Description
PCR[228]
VDDEH7
-/-
-/-
70
100
123
F14
-- --
VDDEH7 VDDEH7
TMS / Up JCOMP / Down
TMS / Up JCOMP / Down
75 69
108 98
131 121
D14 F16
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 PCR[83] PCR PA Field3 01 10 00 01 10 00 01 00 01 00 I/O Type O O22 I/O I I I/O O I/O I I/O O22 O I/O I O I/O I/O I/O I I/O Reset State5 - / Up Function / State After Reset6 - / Up23 Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA 46 66 81 P12
Pinout and Signal Description
40 Name Function1 CNTX_A TXD_A GPIO[83] CNRX_A RXD_A GPIO[84] CNTX_C GPIO[87] CNRX_C GPIO[88] CAN_A Transmit eSCI_A Transmit GPIO CAN_A Receive eSCI_A Receive GPIO CAN_C Transmit GPIO CAN_C Receive GPIO Preliminary--Subject to Change Without Notice Freescale Semiconductor Monaco 1.5M Data Sheet, Rev. 2 TXD_A eMIOS[13] GPIO[89] RXD_A eMIOS[15] GPIO[90] TXD_B GPIO[91] RXD_B GPIO[92] eSCI_A Transmit eMIOS Channel GPIO eSCI_A Receive eMIOS Channel GPIO eSCI_B Transmit GPIO eSCI_B Receive GPIO SCK_B PCS_C[1] GPIO[102] SIN_B PCS_C[2] GPIO[103] SOUT_B PCS_C[5] GPIO[104] PCS_B[0] GPIO[105] DSPI_B Clock DSPI_C PCS24 GPIO DSPI_B Data Input DSPI_C PCS GPIO DSPI_B Data Output DSPI_C PCS GPIO DSPI_B PCS GPIO
Voltage
4
VDDEH4b
PCR[84]
VDDEH4b
- / Up
- / Up
47
67
82
R12
PCR[87] PCR[88]
VDDEH6a VDDEH6a
- / Up - / Up
- / Up - / Up
60 59
84 81
101 98
K13 L14
eSCI PCR[89] 01 10 00 01 10 00 01 00 01 00 VDDEH6a - / Up - / Up -- 83 100 J14
PCR[90]
VDDEH6a
- / Up
- / Up
--
82
99
K14
PCR[91] PCR[92]
VDDEH6a VDDEH6a
- / Up - / Up
- / Up - / Up
-- --
72 69
87 84
L13 M13
DSPI PCR[102] 01 10 00 01 10 00 01 10 00 01 00 I/O O I/O I O I/O O O I/O I/O I/O VDDEH6b - / Up - / Up 64 89 106 J16
PCR[103]
VDDEH6b
- / Up
- / Up
67
95
112
G15
PCR[104]
VDDEH6b
- / Up
- / Up
--
96
113
G13
PCR[105]
VDDEH6b
- / Up
- / Up
--
94
111
G16
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 PCR[106] PCR[107] PCR PA Field3 01 00 01 10 00 01 10 00 01 10 00 01 10 00 I/O Type O I/O O O I/O O I I/O O I/O I/O O I/O I/O Reset State5 - / Up - / Up Function / State After Reset6 - / Up - / Up Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA -- -- 92 90 109 107 H16 H15
Freescale Semiconductor Preliminary--Subject to Change Without Notice 41 Monaco 1.5M Data Sheet, Rev. 2
Name
Function1
Voltage
4
PCS_B[1] GPIO[106] PCS_B[2] SOUT_C GPIO[107] PCS_B[3] SIN_C GPIO[108] PCS_B[4] SCK_C GPIO[109] PCS_B[5] PCS_C[0] GPIO[110]
DSPI_B PCS GPIO DSPI_B PCS DSPI_C Data Output GPIO DSPI_B PCS DSPI_C Data Input GPIO DSPI_B PCS DSPI_C Clock GPIO DSPI_B PCS DSPI_C PCS GPIO
VDDEH6b VDDEH6b
PCR[108]
VDDEH6b
- / Up
- / Up
68
97
114
G14
PCR[109]
VDDEH6b
- / Up
- / Up
63
88
105
H14
PCR[110]
VDDEH6b
- / Up
- / Up
--
87
104
J13
eQADC AN[0] DAN0+ AN[1] DAN0AN[2] DAN1+ AN[3] DAN1AN[4] DAN2+ AN[5] DAN2AN[6] DAN3+ Single Ended Analog Input Positive Terminal Differential Input Single Ended Analog Input Negative Terminal Differential Input Single Ended Analog Input Positive Terminal Differential Input Single Ended Analog Input Negative Terminal Differential Input Single Ended Analog Input Positive Terminal Diff. Input Single Ended Analog Input Negative Terminal Differential Input Single Ended Analog Input Positive Terminal Differential Input -- -- I I I I I I I I I I I I I I VDDA I/AN[0] / 99 143 172 B5
--
--
VDDA
I/-
AN[1] / -
98
142
171
A6
--
--
VDDA
I/-
AN[2] / -
97
141
170
D6
--
--
VDDA
I/-
AN[3] / -
96
140
169
C7 Pinout and Signal Description
-- --
-- --
VDDA VDDA
I/I/-
AN[4] / AN[5] / -
95 94
139 138
168 167
B6 A7
--
--
VDDA
I/-
AN[6] / -
93
137
166
D7
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 -- PCR PA Field3 -- I/O Type I I I I I I I I I O O O I O O O I O O I I O O I I I I I I I Reset State5 I/Function / State After Reset6 AN[7] / Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA 92 136 165 C8
Pinout and Signal Description
42 Name Function1 AN[7] DAN3AN[8]-AN[38]ANW AN[9] ANX AN[10]-AN[39]-ANY Monaco 1.5M Data Sheet, Rev. 2 AN[11] ANZ ETPU_A[19] AN[12] MA[0] SDS ETPU_A[21] AN[13] MA[1] SDO ETPU_A[27] AN[14] MA[2] SDI ETPU_A[29] AN[15] FCK Freescale Semiconductor AN[16] AN[17] AN[18] AN[21] AN[22] AN[23] AN[24] Preliminary--Subject to Change Without Notice
Voltage
4
Single Ended Analog Input Negative Terminal Differential Input Single Ended Analog Input Multiplexed Analog Input Single Ended Analog Input External Multiplexed Analog Input Single Ended Analog Input Multiplexed Analog Input Single Ended Analog Input External Multiplexed Analog Input Single Ended Analog Input ETPU_A Channel Mux Address eQADC Serial Data Strobe Single Ended Analog Input ETPU_A Channel Mux Address eQADC Serial Data Out Single Ended Analog Input ETPU_A Channel Mux Address eQADC Serial Data In
VDDA
-- --
-- --
VDDA VDDA
I/I/-
AN[38] / AN[9] / -
6 2
9 5
9 5
B3 A2
-- --
-- --
VDDA VDDA
I/I/-
AN[39] / AN[11] / -
5 1
8 4
8 4
D2 A3
PCR[215]
01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 -- -- -- -- -- -- --
VDDEH7
I/-
AN[12] / -
81
119
148
A12
PCR[216]
VDDEH7
I/-
AN[13] / -
80
118
147
B12
PCR[217]
VDDEH7
I/-
AN[14] / -
79
117
146
C12
Single Ended Analog Input PCR[218] ETPU_A Channel eQADC Free Running Clock Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input -- -- -- -- -- -- --
VDDEH7
I/-
AN[15] / -
78
116
145
C13
VDDA VDDA VDDA VDDA VDDA VDDA VDDA
I/I/I/I/I/I/I/-
AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / -
-- -- -- 100 -- 88 --
3 2 1 144 132 131 130
3 2 1 173 161 160 159
C6 C4 D5 B4 B8 C9 D8
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PCR PA Field3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O Type I I I I I I I I I I I I I I I I eTPU2 eTPU_A[0] eTPU_A[12] eTPU_A[19] GPIO[114] eTPU_A[1] eTPU_A[13] GPIO[115] eTPU_A[2] eTPU_A[14] GPIO[116] eTPU_A[3] eTPU_A[15] GPIO[117] eTPU_A Channel eTPU_A Channel eTPU_A Channel GPIO eTPU_A Channel eTPU_A Channel GPIO eTPU_A Channel eTPU_A Channel GPIO eTPU_A Channel eTPU_A Channel GPIO PCR[114] 011 010 100 000 01 10 00 01 10 00 01 10 00 I/O O O I/O I/O O I/O I/O O I/O I/O O I/O VDDEH4a -/ WKPCFG - / WKPCFG 37 52 61 L4, N3 Reset State5 I/I/I/I/I/I/I/I/I/I/I/I/I/-/-/-/Function / State After Reset6 AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / AN[x] / AN[38] / AN[39] / VRH VRL REFBYPC Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA 87 -- 86 -- 85 -- 84 -- 83 -- -- 6 5 90 89 91 129 128 127 126 125 124 123 122 121 -- -- 9 8 134 133 135 158 157 156 155 154 153 152 151 150 1747 1757 9 8 163 162 164 B9 A10 B10 D9 D10 C10 C11 C5 D11 -- E38 B3 D2 A8 A9 B7
Freescale Semiconductor Preliminary--Subject to Change Without Notice 43 Monaco 1.5M Data Sheet, Rev. 2
Name
Function1
Voltage
4
AN[25] AN[27] AN[28] AN[30] AN[31] AN[32] AN[33] AN[34] AN[35] AN[36] AN[37] AN[38]-AN[8]ANW AN[39]-AN[10]-ANY VRH VRL REFBYPC
Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Single Ended Analog Input Multiplexed Analog Input Single Ended Analog Input Multiplexed Analog Input Voltage Reference High Voltage Reference Low Bypass Capacitor Input
VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VSSA0 VRL
Pinout and Signal Description
PCR[115]
VDDEH4a
-/ WKPCFG -/ WKPCFG -/ WKPCFG
- / WKPCFG
36
51
60
M3
PCR[116]
VDDEH4a
- / WKPCFG
35
50
59
P2
PCR[117]
VDDEH4a
- / WKPCFG
34
49
58
P1
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 PCR[118] PCR PA Field3 01 10 00 001 010 100 000 001 010 100 000 0001 0010 0100 1000 0000 001 010 100 000 01 10 00 01 10 00 01 10 00 01 10 00 01 10 00 I/O Type I/O O I/O I/O O O I/O I/O O O I/O I/O O O O I/O I/O O O I/O I/O O I/O I/O O I/O I/O O I/O I/O O I/O I/O O I/O Reset State5 -/ WKPCFG -/ WKPCFG Function / State After Reset6 - / WKPCFG Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA 32 47 56 N2
Pinout and Signal Description
44 Name Function1 eTPU_A[4] eTPU_A[16] GPIO[118] eTPU_A[5] eTPU_A[17] SCK_B_LVDS+ GPIO[119] eTPU_A[6] eTPU_A[18] SCK_B_LVDSGPIO[120] eTPU_A[7] eTPU_A[19] SOUT_B_LVDS+ eTPU_A[6] GPIO[121] eTPU_A[8] eTPU_A[20] SOUT_B_LVDSGPIO[122] eTPU_A[9] eTPU_A[21] GPIO[123] eTPU_A[10] eTPU_A[22] GPIO[124] eTPU_A[11] eTPU_A[23] GPIO[125] eTPU_A[12] PCS_B[1] GPIO[126] eTPU_A[13] PCS_B[3] GPIO[127] eTPU_A Channel eTPU_A Channel GPIO eTPU_A Channel eTPU_A Channel SCK_B LVDSGPIO eTPU_A Channel eTPU_A Channel SCK_B LVDS+ GPIO eTPU_A Channel eTPU_A Channel SOUT_B LVDSeTPU_A channel GPIO eTPU_A Channel eTPU_A Channel SOUT_B LVDS+ GPIO eTPU_A Channel eTPU_A Channel GPIO eTPU_A Channel eTPU_A Channel GPIO eTPU_A Channel eTPU_A Channel GPIO eTPU_A Channel DSPI_B PCS GPIO eTPU_A Channel DSPI_B PCS GPIO Preliminary--Subject to Change Without Notice Freescale Semiconductor Monaco 1.5M Data Sheet, Rev. 2
Voltage
4
VDDEH4a
PCR[119]
VDDEH4a
- / WKPCFG
30
45
54
M4
PCR[120]
VDDEH4a
-/ WKPCFG
- / WKPCFG
29
44
53
L3
PCR[121]
VDDEH4a
-/ WKPCFG
- / WKPCFG
28
43
52
K3
PCR[122]
VDDEH4a
-/ WKPCFG
- / WKPCFG
27
42
51
N1
PCR[123]
VDDEH4a
-/ WKPCFG -/ WKPCFG -/ WKPCFG -/ WKPCFG -/ WKPCFG
- / WKPCFG
--
41
50
M2
PCR[124]
VDDEH1b
- / WKPCFG
--
40
49
M1
PCR[125]
VDDEH1b
- / WKPCFG
--
39
48
L2
PCR[126]
VDDEH1b
- / WKPCFG
--
38
47
L1
PCR[127]
VDDEH1b
- / WKPCFG
26
37
46
J4
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 PCR[128] PCR PA Field3 001 010 100 000 01 10 00 01 00 01 00 01 00 01 00 01 10 00 01 10 00 001 010 100 000 001 010 100 000 001 010 100 000 I/O Type I/O O O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I I/O I/O I O I/O I/O I O I/O O I I/O I/O Reset State5 -/ WKPCFG Function / State After Reset6 - / WKPCFG Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA 24 35 42 J3
Freescale Semiconductor Preliminary--Subject to Change Without Notice 45 Monaco 1.5M Data Sheet, Rev. 2
Name
Function1
Voltage
4
eTPU_A[14] PCS_B[4] eTPU_A[9] GPIO[128] eTPU_A[15] PCS_B[5] GPIO[129] eTPU_A[16] GPIO[130] eTPU_A[17] GPIO[131] eTPU_A[18] GPIO[132] eTPU_A[19] GPIO[133] eTPU_A[20] IRQ[8] GPIO[134] eTPU_A[21] IRQ[9] GPIO[135] eTPU_A[22] IRQ[10] eTPU_A[17] GPIO[136] eTPU_A[23] IRQ[11] eTPU_A[21] GPIO[137] eTPU_A[24] IRQ[12] SCK_C_LVDS+ GPIO[138]
eTPU_A Channel DSPI_B Periph Chip Select eTPU_A Channel GPIO eTPU_A Channel DSPI_B Periph Chip Select GPIO eTPU_A Channel GPIO eTPU_A Channel GPIO eTPU_A Channel GPIO eTPU_A Channel GPIO eTPU_A Channel External Interrupt Request GPIO eTPU_A Channel External Interrupt Request GPIO eTPU_A Channel External External Interrupt Request eTPU_A Channel External GPIO eTPU_A Channel External External Interrupt Request eTPU_A Channel External GPIO eTPU_A Channel External External Interrupt Request SCK_C LVDSGPIO
VDDEH1b
PCR[129]
VDDEH1b
-/ WKPCFG -/ WKPCFG -/ WKPCFG -/ WKPCFG -/ WKPCFG -/ WKPCFG -/ WKPCFG -/ WKPCFG
- / WKPCFG
22
33
40
K2
PCR[130] PCR[131] PCR[132] PCR[133] PCR[134]
VDDEH1b VDDEH1b VDDEH1b VDDEH1b VDDEH1b
- / WKPCFG - / WKPCFG - / WKPCFG - / WKPCFG - / WKPCFG
-- -- -- -- --
32 31 30 29 28
39 38 37 36 35
K1 H3 H4 J2 J1
PCR[135]
VDDEH1a
- / WKPCFG
--
27
34
G4
PCR[136]
VDDEH1a
- / WKPCFG
--
25
32
H2
PCR[137]
VDDEH1a
-/ WKPCFG
- / WKPCFG
--
23
30
H1
Pinout and Signal Description
PCR[138]
VDDEH1a
-/ WKPCFG
- / WKPCFG
18
21
28
G1
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 PCR[139] PCR PA Field3 001 010 100 000 001 010 100 000 0001 0010 0100 1000 0000 10 01 00 10 01 00 011 010 001 000 011 010 001 000 011 000 011 000 011 000 I/O Type O I I/O I/O O I O I/O O I O I/O O O I/O O O I/O I/O O O I/O I/O O O I/O O I/O O I/O O I/O Reset State5 -/ WKPCFG Function / State After Reset6 - / WKPCFG Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA 17 20 27 G3
Pinout and Signal Description
46 Name Function1 eTPU_A[25] IRQ[13] SCK_C_LVDSGPIO[139] eTPU_A[26] IRQ[14] SOUT_C_LVDS+ GPIO[140] eTPU_A[27] IRQ[15] SOUT_C_LVDSSOUTB GPIO[141] eTPU_A[28] PCS_C[1] GPIO[142] eTPU_A[29] PCS_C[2] GPIO[143] eTPU_A[30] PCS_C[3] eTPU_A[11] GPIO[144] eTPU_A[31] PCS_C[4] eTPU_A[13] GPIO[145] eTPU_A[2]_O GPIO[231] eTPU_A[4]_O GPIO[277] eTPU_A[13]_O GPIO[220] Preliminary--Subject to Change Without Notice Freescale Semiconductor Monaco 1.5M Data Sheet, Rev. 2 eTPU_A Channel (Output Only) DSPI_C PCS GPIO eTPU_A Channel (Output Only) DSPI_C PCS GPIO eTPU_A Channel DSPI_C PCS eTPU_A Channel GPIO eTPU_A Channel DSPI_C PCS eTPU_A Channel GPIO eTPU_A Channel GPIO eTPU_A Channel GPIO eTPU_A Channel GPIO
Voltage
4
eTPU_A Channel External External Interrupt Request SCK_C LVDS+ GPIO eTPU_A Channel External External Interrupt Request SOUT_C LVDSGPIO eTPU_A Channel External Interrupt Request SOUT_C LVDS+ SOUTB GPIO
VDDEH1a
PCR[140]
VDDEH1a
-/ WKPCFG
- / WKPCFG
16
19
26
F3
PCR[141]
VDDEH1a
-/ WKPCFG
- / WKPCFG
15
18
25
G2
PCR[142]
VDDEH1a
-/ WKPCFG
- / WKPCFG
14
17
24
F1
PCR[143]
VDDEH1a
-/ WKPCFG
- / WKPCFG
13
16
23
F2
PCR[144]
VDDEH1a
-/ WKPCFG
- / WKPCFG
12
15
22
E1
PCR[145]
VDDEH1a
-/ WKPCFG
- / WKPCFG
11
14
21
E2
PCR[231] PCR[277] PCR[220]
VDDEH7 VDDEH7 VDDEH7
-/-/-/-
-/-/-/-
-- -- --
-- -- --
126 129 135
P10 T10 T11
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 PCR[221] PCR[222] PCR[223] PCR[224] PCR[225] PCR PA Field3 011 000 011 000 011 000 011 000 011 000 I/O Type O I/O O I/O O I/O O I/O O I/O Reset State5 -/-/-/-/-/Function / State After Reset6 -/-/-/-/-/Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA -- -- -- -- -- -- -- -- -- -- 136 137 139 134 124 N11 P11 T7 R10 P9
Freescale Semiconductor Preliminary--Subject to Change Without Notice 47 Monaco 1.5M Data Sheet, Rev. 2
Name
Function1
Voltage
4
eTPU_A[19]_O GPIO[221] eTPU_A[21]_O GPIO[222] eTPU_A[25]_O GPIO[223] eTPU_A[27]_O GPIO[224] eTPU_A[29]_O GPIO[225]
eTPU_A Channel GPIO eTPU_A Channel GPIO eTPU_A Channel GPIO eTPU_A Channel GPIO eTPU_A Channel GPIO
VDDEH7 VDDEH7 VDDEH7 VDDEH7 VDDEH7
eMIOS eMIOS[0] eTPU_A[0] eTPU_A[25] GPIO[179] eMIOS[1] eTPU_A[1] GPIO[180] eMIOS[2] eTPU_A[2] GPIO[181] eMIOS[4] eTPU_A[4] GPIO[183] eMIOS[8] eTPU_A[8] TXDB GPIO[187] eMIOS[9] eTPU_A[9] RXDB GPIO[188] eMIOS[10] GPIO[189] eMIOS Channel eTPU_A Channel eTPU_A Channel GPIO eMIOS Channel eTPU_A Channel GPIO eMIOS Channel eTPU_A Channel GPIO eMIOS Channel eTPU_A Channel GPIO eMIOS Channel eTPU_A Channel eSCI_B Transmit GPIO eMIOS Channel eTPU_A Channel eSCI_B Receive GPIO eMIOS Channel GPIO PCR[179] 001 010 100 000 01 10 00 01 10 00 01 10 00 001 010 100 000 001 010 100 000 01 00 I/O O O I/O I/O O I/O I/O O I/O I/O O I/O I/O O O I/O I/O O I I/O I/O I/O VDDEH4a -/ WKPCFG - / WKPCFG 39 54 63 T4
PCR[180]
VDDEH4b
-/ WKPCFG -/ WKPCFG -/ WKPCFG -/ WKPCFG
- / WKPCFG
--
--
647
T58
PCR[181]
VDDEH4b
- / WKPCFG
--
55
65
N7
PCR[183]
VDDEH4b
- / WKPCFG
--
56
67
R5
PCR[187]
VDDEH4b
- / WKPCFG
40
57
70
P8 Pinout and Signal Description
PCR[188]
VDDEH4b
-/ WKPCFG
- / WKPCFG
41
58
71
R7
PCR[189]
VDDEH4b
-/ WKPCFG
- / WKPCFG
--
60
73
N8
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 PCR[190] PCR[191] PCR PA Field3 01 00 001 010 100 000 01 00 001 010 100 000 01 10 00 01 00 I/O Type I/O I/O O O O I/O I/O I/O O I O I/O O I I/O I/O I/O Reset State5 -/ WKPCFG -/ WKPCFG Function / State After Reset6 - / WKPCFG - / WKPCFG Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA -- 44 62 63 75 76 R8 N10
Pinout and Signal Description
48 Name Function1 eMIOS[11] GPIO[190] eMIOS[12] DSPI_C_SOUT eTPU_A[27] GPIO[191] eMIOS[13] GPIO[192] eMIOS[14] IRQ[0] eTPU_A[29] GPIO[193] eMIOS[15] IRQ[1] GPIO[194] eMIOS[23] GPIO[202] eMIOS Channel GPIO eMIOS Channel DSPI C Data Output eTPU_A Channel GPIO eMIOS Channel GPIO Preliminary--Subject to Change Without Notice Freescale Semiconductor Monaco 1.5M Data Sheet, Rev. 2 eMIOS Channel GPIO XTAL EXTAL EXTCLK CLKOUT Crystal Oscillator Output Crystal Oscillator Input External Clock Input System Clock Output VDDPLL VSSPLL27 VSTBY VRC33 VRCCTL PLL Supply Voltage PLL Ground Power Supply for Standby RAM 3.3V Voltage Regulator Bypass Capacitor Voltage Regulator Control Output
Voltage
4
VDDEH4b VDDEH4b
PCR[192] PCR[193]
VDDEH4b VDDEH4b
-/ WKPCFG -/ WKPCFG
- / WKPCFG - / WKPCFG
-- 45
-- 64
777 78
T88 R9
eMIOS Channel External Interrupt Request eTPU_A Channel GPIO eMIOS Channel External Interrupt Request GPIO
PCR[194]
VDDEH4b
-/ WKPCFG -/ WKPCFG
- / WKPCFG
--
--
797
T98
PCR[202]
VDDEH4b
- / WKPCFG
--
65
80
R11
Clock Synthesizer -- -- PCR[229] -- -- -- O I O VDDEH6a VDDEH6a VDDE12 O/I/CLKOUT / Enabled XTAL25 / EXTAL26/ CLKOUT / Enabled 54 53 -- 76 75 -- 93 92 -- P16 N16 T14
Power / Ground -- -- -- -- -- -- -- -- -- -- I I I O O VDDPLL (1.2V) VSSPLL VSTBY VRC33 NA I/I/I/O/O/-- -- -- -- -- 52 55 9 10 8 74 77 12 13 11 91 94 12 13 11 R16 M16 C1 A15, D1, N6, N12 N14
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 -- -- -- -- -- -- -- -- PCR PA Field3 -- -- -- -- -- -- -- -- I/O Type I I I I I I I I Reset State5 I/I/I/I/I/I/I/I/Function / State After Reset6 -- -- -- -- -- -- -- Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA 3 -- -- -- -- 4 7 21, 38, 62, 82 6 -- -- -- -- 7 10 26, 53, 86, 120 6 -- -- -- -- 7 10 33, 62, 103, 149 -- B11 A11 A4 A5 -- K16 B1, B16, C2, D3, E4, N5, P4, P13, R3, R14, T2, T15
Freescale Semiconductor Preliminary--Subject to Change Without Notice 49 Monaco 1.5M Data Sheet, Rev. 2
Name VDDA28 VDDA0 VSSA0 VDDA1 VSSA1 VSSA29 VDDREG VDD
Function1
Voltage
4
Analog Power Input for eQADC Analog Power Input for eQADC Analog Ground Input for eQADC Analog Power Input for eQADC Analog Ground Input for eQADC Analog Ground Input for eQADC Voltage Regulator Supply Internal Logic Supply Input
VDDA (5.0 V) VDDA VSSA VDDA VSSA VSSA VDDREG (5.0 V) VDD (1.2 V)
VSS
Ground
--
--
-
VSS0
I/-
-
19, 25, 33, 42, 57, 65, 72, 77
22, 36, 48, 59, 73, 79, 91, 104, 115
A1, A16, 157, B2, B15, 29, C3, C14, 43, D4, D13, 57, G7, G8, 72, G9, G10, 90, H7, H8, 96, 108, H9, H10, 1157, J7, J8, J9, 127, J10, K7, 1337, K8, K9, 144 K10, N4, N13, P3, P14, R2, R15, T1, T16
Pinout and Signal Description
Table 3. MPC563xM Signal Properties (continued)
Pad Config. Register (PCR)2 -- -- PCR PA Field3 -- -- I/O Type -- I Reset State5 I/I/Function / State After Reset6 Pin No. 144 176 208 MAP 100 LQFP LQFP LQFP BGA -- -- 167, 1197 E13, P6, T13 --
Pinout and Signal Description
50 Name VDDE1230 VDDEH1A VDDEH1B Preliminary--Subject to Change Without Notice Freescale Semiconductor VSSE1A VSSE1B VDDEH4 VDDEH4A VDDEH4B VSSE4a VSSE4b VDDE5 VDDEH6a32 VDDEH6b VDDEH6 VSSE6a VSSE6b VDDEH7 I/O Supply Input I/O Ground Input I/O Supply Input Monaco 1.5M Data Sheet, Rev. 2 Function1 Voltage regulator output I/O Supply Input I/O Ground Input I/O Supply Input I/O Supply Input I/O Ground Input I/O Supply Input I/O Supply Input VDDE7 VSSE7
1 2 3 4 5
Voltage
4
VDDE12 (3.3V ) VDDEH131 (3.3V 5.0V) VSSEH1 VDDEH4
20, 23 24, 34 31, 41
-- -- --
-- -- --
I
I/I/-
-- --
-- --
-- --
-- N9 --
I
VDDEH431 (3.3V 5.0V) VSSEH4 VDDE5 VDDEH6 (3.3V 5.0V) VDDEH6 VSSEH6 VDDEH733 (3.3V 5.0V) VDDE7 VSSE7
31, 43 46, 61 55, 74
-- -- --
-- -- --
I I I
I/I/-
-- --
-- --
-- -- 95, 110 -- -- 125, 138 -- --
-- T13 --
56 ,66 78, 93
-- -- --
-- -- --
I I I
I/-
-
-- -- 71, 76
-- -- 102, 113 -- --
F13 -- D12
I/-
-
I/O Supply Input I/O Ground Input
-- --
-- --
I I
I/-
-
-- --
P6, E13 --
For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary function or GPIO is done in the SIU except where explicitly noted. Values in this column refer to registers in the System Integration Unit (SIU). The actual register name is "SIU_PCR" suffixed by the PCR number. For example, PCR[190] refers to the SIU register named SIU_PCR190. The Pad Configuration Register (PCR) PA field is used by software to select pin function. The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V range (+/- 10%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/- 10%). Terminology is O - output, I - input, Up - weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. A dash for the function in this column denotes that both the input and output buffer are turned off.
6 7
Function after reset of GPI is general purpose input. A dash for the function in this column denotes that both the input and output buffer are turned off. Not available on 1 MB version of 176-pin package. 8 Not available on 1 MB version of 208-pin package. 9 Signals in this section are available only on calibration package. 10 On the calibration package, the Nexus function on this pin is enabled when the NEXUSCFG pin is high and Nexus is configured to full port mode. On the 208-pin package, the Nexus function on this pin is enabled permanently. 11 In the calibration package, the I/O segment containing this pin is called VDDE12. 12 In the 208-pin package, the I/O segment containing this pin is called VDDE7 13 When configured as Nexus (208-pin package or calibration package with NEXUSCFG=1), and JCOMP is asserted during reset, MDO[0] is driven high until the crystal oscillator becomes stable, at which time it is then negated. 14 The function of this pin is Nexus when NEXUSCFG is high. 15 High when the pin is configured to Nexus, low otherwise. 16 O/Low for the calibration with NEXUSCFG=0; I/Up otherwise. 17 CAL_ADDR/Low for the calibration package with NEXUSCFG=0; EVTI/Up otherwise. 18 The primary function is not selected via the PA field when the pin is a Nexus signal. Instead, it is activated by the Nexus controller. 19 If JCOMP is asserted during reset, MDO[0] is driven high until the crystal oscillator becomes stable, at which time it is then negated. 20 TDI and TDO are required for JTAG operation. 21 The primary function is not selected via the PA field when the pin is a JTAG signal. Instead, it is activated by the JTAG controller. 22 From the user point of view this is an output pad; to implement the CAN protocol this pad must also implement the input direction. 23 The function and state of the CAN_A and eSCI_A pins after execution of the BAM program is determined by the BOOTCFG pin. 24 Peripheral chip select (PCS). 25 The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has no function and should be grounded. 26 The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen, the valid operating voltage for the pin is 1.62 V to 3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V. 27 VSSPLL and VSSREG are connected to the same pin. 28 This pin is shared by two pads: VDDA_AN, using pad_vdde_hv, and VDDA_DIG, using pad_vdde_int_hv. 29 This pin is shared by two pads: VSSA_AN, using pad_vsse_hv, and VSSA_DIG, using pad_vsse_int_hv. 30 VDD12/VSS12 pins are to be used for decoupling capacitors only. 31 LVDS pins will not work at 3.3 V. 32 The VDDEH6 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for analog input function. 33 If using JTAG or Nexus, the I/O segment that contains the JTAG and Nexus pins must be powered by a 5 V supply. The 3.3 V Nexus/JTAG signals are derived from the 5 volt power supply.
Freescale Semiconductor Preliminary--Subject to Change Without Notice 51 Monaco 1.5M Data Sheet, Rev. 2
Pinout and Signal Description
Electrical Characteristics
3
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC5634M series of MCUs. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" for System Requirement is included in the Symbol column.
3.1
Maximum Ratings
Table 4. Absolute Maximum Ratings1
Value2 Symbol Parameter 1.2 V core supply voltage3 Flash core voltage4,5 SRAM standby voltage6 Clock synthesizer voltage3 Conditions min VDD VFLASH VSTBY VDDPLL VRC337 VDDA VDDE VDDEH VIN SR SR SR SR SR SR SR SR SR - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 Reference to VSSA - 0.3 - 0.3 - 0.3 VDDEH powered I/O pads VDDE powered I/O pads VDDREG VRH VSS - VSSA VRH - VRL VRL - VSSA SR SR SR SR SR Voltage regulator supply voltage6 Analog reference high voltage6 VSS differential voltage VREF differential voltage6 VRL to VSSA differential voltage Reference to VRL -1.010 -1.010 - 0.3 - 0.3 - 0.1 - 0.3 - 0.3 max 1.32 3.6 5.5 1.32 3.6 5.5 3.6 5.5 VDDEH + 0.3 V11 VDDE + 0.3 V12 5.5 5.5 0.1 5.5 0.3 V V V V V V V V V V V V V V Unit
Voltage regulator control input voltage5 Analog supply voltage6 I/O supply voltage5,8 I/O supply voltage6,8 DC input voltage9
MPC5634M Microcontroller Data Sheet, Rev. 2 52 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 4. Absolute Maximum Ratings1 (continued)
Value2 Symbol Parameter Conditions min VSSPLL - VSS IMAXD IMAXA TJ SR SR SR SR VSSPLL to VSS differential voltage Maximum DC digital input current13 Maximum DC analog input current14 Maximum operating temperature range16 - die junction temperature Storage temperature range Maximum solder temperature17 Moisture sensitivity level18 Per pin, applies to all digital pins Per pin, applies to all analog pins - 0.1 -3 -- - 40.0 max 0.1 3 50 mA15 150.0 V mA mA
o
Unit
C
TSTG TSDR MSL
1
SR SR SR
- 55.0 --
150.0 235.0 3
oC
oC
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 TBD: To Be Defined. 3 Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%. 4 The V FLASH supply is connected to VRC33 in the package substrate. This specification applies to calibration package devices only. 5 Allowed 5.3 V for 10 hours cumulative time, remaining time at 3.3 V +10%. 6 Allowed 5.9 V for 10 hours cumulative time, remaining time at 5 V +10%. 7 The pin named as V RC33 is internally connected to the pads VFLASH and VRC33 in the 144 LQFP package. These limits apply when the internal regulator is disabled and VRC33 power is supplied externally. 8 All functional non-supply I/O pins are clamped to V SS and VDDE, or VDDEH. 9 AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 10 Internal structures hold the voltage greater than -1.0 V if the injection current limit of 2 mA is met. 11 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDEH supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications. 12 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications. 13 Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 14 Total injection current for all analog input pins must not exceed 15 mA. 15 During maximum trim. 16 Lifetime operation at these specification limits is not guaranteed. 17 Solder profile per IPC/JEDEC J-STD-020D. 18 Moisture sensitivity per JEDEC test method A112.
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 53
Electrical Characteristics
3.2
Thermal Characteristics
Table 5. Thermal Characteristics for 100-pin LQFP1
Symbol RJA RJA RJMA RJMA RJB RJCtop JT
1 2 3 4
Parameter CC CC CC CC CC CC CC Junction-to-Ambient, Natural Convection2 Junction-to-Ambient, Natural Convection2 Junction-to-Ambient2 Junction-to-Ambient2 Junction-to-Board3 Junction-to-Case (Top)4 Junction-to-Package Top, Natural Convection5
Conditions Single layer board - 1s Four layer board 2s2p @200 ft./min., single layer board @200 ft./min., four layer board 2s2p
Value 47 35 37 29 20 9 2
Unit C/W C/W C/W C/W C/W C/W C/W
5
Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Table 6. Thermal Characteristics for 144-pin LQFP1
Symbol RJA RJA RJMA RJMA RJB RJCtop JT
1
Parameter CC CC CC CC CC CC CC Junction-to-Ambient, Natural Convection2 Junction-to-Ambient, Natural Convection2 Junction-to-Ambient2 Junction-to-Ambient2 Junction-to-Board3 Junction-to-Case4 Junction-to-Package Top, Natural Convection5
Conditions Single layer board - 1s Four layer board - 2s2p @200 ft./min., single layer board @200 ft./min., four layer board 2s2p
Value 43 35 34 29 22 8 2
Unit C/W C/W C/W C/W C/W C/W C/W
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
MPC5634M Microcontroller Data Sheet, Rev. 2 54 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Table 7. Thermal Characteristics for 176-pin LQFP1
Symbol RJA RJA RJMA RJMA RJB RJCtop JT
1 2 3 4
Parameter CC CC CC CC CC CC CC Junction-to-Ambient, Natural Convection2 Junction-to-Ambient, Natural Convection2 Junction-to-Ambient2 Junction-to-Ambient2 Junction-to-Board3 Junction-to-Case4 Junction-to-Package Top, Natural Convection5
Conditions Single layer board - 1s Four layer board - 2s2p @200 ft./min., single layer board - 1s @200 ft./min., four layer board - 2s2p
Value 43 36 35 30 25 9 2
Unit C/W C/W C/W C/W C/W C/W C/W
5
Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Table 8. Thermal Characteristics for 208-pin MAPBGA1
Symbol RJA RJMA RJA CC CC CC Parameter Junction-to-ambient, natural convection2,3 Junction-to-ambient natural convection2,4 Junction-to-ambient2,4 Conditions One layer board - 1s Four layer board 2s2p @200 ft./min., one layer board Value 39 24 31 Unit C/W C/W C/W
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 55
Electrical Characteristics
Table 8. Thermal Characteristics for 208-pin MAPBGA1 (continued)
Symbol RJMA RJB RJC JT
1 2
Parameter CC CC CC CC Junction-to-ambient2,4 Junction-to-board5 Junction-to-case6 Junction-to-package top natural convection7
Conditions @200 ft./min., four layer board 2s2p Four layer board 2s2p
Value 20 13 6 2
Unit C/W C/W C/W C/W
3 4 5 6
7
Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
3.2.1
General Notes for Specifications at Maximum Junction Temperature
TJ = TA + (RJA * PD) Eqn. 1
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
where: TA = ambient temperature for the package (oC) RJA = junction-to-ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: * * * * Construction of the application board (number of planes) Effective size of the board which cools the component Quality of the thermal and electrical connections to the planes Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
MPC5634M Microcontroller Data Sheet, Rev. 2 56 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: * * * One oz. (35 micron nominal thickness) internal planes Components are well separated Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB * PD) where: TB = board temperature for the package perimeter (oC) RJB = junction-to-board thermal resistance (oC/W) per JESD51-8S PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (oC/W) RJC = junction-to-case thermal resistance (oC/W) RCA = case to ambient thermal resistance (oC/W) RJC s device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT = thermocouple temperature on top of the package (oC) Eqn. 4 Eqn. 3 Eqn. 2
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 57
Electrical Characteristics
JT PD
= thermal characterization parameter (oC/W) = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134 USA (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. * * * C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. G. Kromann, S. Shidore, and S. Addison, "Thermal Modeling of a PBGA for Air-Cooled Applications", Electronic Packaging and Production, pp. 53-58, March 1998. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
3.3
EMI (Electromagnetic Interference) Characteristics
Table 9. EMI Testing Specifications1
Symbol Radiated emissions, electric field Parameter VRE_TEM Conditions VDD = 5.5 V TA = +25 C fOSC/fBUS 16 MHz crystal 40 MHz bus No PLL frequency modulation Frequency 0.15 - 50 MHz 50 - 150 MHz 150 - 500 MHz 500 - 1000 MHz IEC Level SAE Level 16 MHz crystal 40 MHz bus +/-2% PLL frequency modulation 0.15 - 50 MHz 50 - 150 MHz 150 - 500 MHz 500 - 1000 MHz IEC Level SAE Level
1
Level (Max)2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Unit dBV
-- -- dBV
-- --
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03.
MPC5634M Microcontroller Data Sheet, Rev. 2 58 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2
TBD: To Be Defined.
3.4
Electromagnetic Static Discharge (ESD) Characteristics
Table 10. ESD Ratings1,2
Symbol -- R1 C -- SR SR SR SR ESD for field induced charge Model (FDCM) Number of pulses per pin Parameter ESD for Human Body Model (HBM) HBM circuit description -- -- -- All pins Corner pins Positive pulses (HBM) Negative pulses (HBM) --
1
Conditions
Value 2000 1500 100 500 750 1 1 1
Unit V
pF V
--
SR
-- -- --
SR
Number of pulses
--
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 Device failure is defined as: "If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature."
3.5
Power Management Control (PMC) and Power On Reset (POR) Electrical Specifications
Table 11. PMC Operating Conditions and External Regulators Supply Voltage
Name Jtemp Vddreg Vdd1p2 Ivrcctl Vdd3p3 --
1
Parameter Junction temperature PMC 5 V supply voltage VDDREG Core supply voltage 1.2 V VDD when external regulator is used2 Voltage regulator core supply maximum required DC output current Regulated 3.3 V supply voltage when external regulator is used3 Voltage regulator 3.3 V supply maximum required DC output current
Min -40 4.51 1.2 500 3.3 80
Typ 27 5 1.2 -- 3.3 --
Max 150 5.5 1.32 -- 3.6 --
Unit C V V mA V mA
During start up operation the minimum required voltage to come out of reset state is 4.6 V. An internal regulator controller might be used to regulate core supply. 3 An internal regulator might be used to regulate 3.3 V supply.
2
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 59
Electrical Characteristics
Table 12. PMC Electrical Characteristics
Name Vbg -- -- -- -- Vdd1p2 -- Parameter Nominal bandgap voltage reference Untrimmed bandgap reference voltage Trimmed bandgap reference voltage (5 V, 27 C) Bandgap reference temperature variation Bandgap reference supply voltage variation Nominal VDD core supply internal regulator target DC output voltage1 Nominal VDD core supply internal regulator target DC output voltage variation before band-gap trim Nominal VDD core supply internal regulator target DC output voltage variation after band-gap trim Trimming step Vdd1p2 Voltage regulator controller for core supply maximum DC output current Nominal LVI for rising core supply2,3 Variation of LVI for rising core supply before band gap trim Variation of LVI for rising core supply after band gap trim Trimming step LVI core supply LVI core supply hysteresis POR 1.2 V rising POR 1.2 V rising variation POR 1.2 V falling POR 1.2 V falling variation Nominal 3.3 V supply internal regulator DC output voltage Nominal 3.3 V supply internal regulator DC output voltage variation before band-gap trim Nominal 3.3 V supply internal regulator DC output voltage variation after band-gap trim Voltage regulator 3.3 V output impedance at maximum DC load Voltage regulator 3.3 V maximum DC output current Min -- Vbg-4.5% Vbg-6mV -- -- -- Vdd1p2-6% Typ 1.219 Vbg Vbg 100 1500 1.2 Vdd1p2 Max -- Vbg+4.5% Vbg+6mV -- -- -- Vdd1p2+10% Unit V V V ppm/ C ppm/ V V V
--
Vdd1p2-5%
Vdd1p2
Vdd1p2+10%
V
-- Ivrcctl Lvi1p2 -- -- -- -- Por1.2V_r -- Por1.2V_f -- Vdd3p3 --
-- 20 -- Lvi1p2-6% Lvi1p2-3% -- 36 -- Por1.2V_r-35% -- Por1.2V_f-35% -- Vdd3p3-6%
20 -- 1.080 Lvi1p2 Lvi1p2 20 40 0.709 Por1.2V_r 0.638 Por1.2V_f 3.3 Vdd3p3
-- -- -- Lvi1p2+6% Lvi1p2+3% -- 44 --
mV mA V V V mV mV V
Por1.2V_r+35% V -- V
Por1.2V_f+35% V -- Vdd3p3+10% V V
-- -- Idd3p3
Vdd3p3-5% -- --
Vdd3p3 -- --
Vdd3p3+10% 2 80
V mA
MPC5634M Microcontroller Data Sheet, Rev. 2 60 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 12. PMC Electrical Characteristics (continued)
Name Parameter Min 81 -- Lvi3p3-6% Lvi3p3-3% -- 54 -- Por3.3V_r-35% -- Por3.3V_f-35% -- Lvi5p0-6% Lvi5p0-3% -- 54 -- Por5V_r-35% -- Por5V_f-35% Typ 130 3.090 Lvi3p3 Lvi3p3 20 60 1.96 Por3.3V_r 1.76 Por3.3V_f 4.29 Lvi5p0 Lvi5p0 20 60 2.6 Por5V_r 2.4 Por5V_f Max 187 -- Lvi3p3+6% Lvi3p3+3% -- 66 -- Unit mA V V V mV mV V
vdd3p3 ILim Voltage regulator 3.3 V DC current limit Lvi3p3 -- -- -- -- Por3.3V_r -- Por3.3V_f -- 8 8a 8b 8c 8d 9 9a 9b 9c
1 2
Nominal LVI for rising 3.3 V supply Variation of LVI for rising 3.3 V supply before band gap trim Variation of LVI for rising 3.3 V supply after band gap trim Trimming step LVI 3.3 V LVI 3.3 V hysteresis Nominal POR for rising 3.3 V supply Variation of POR for rising 3.3 V supply Nominal POR for falling 3.3 V supply Variation of POR for falling 3.3 V supply Nominal LVI for rising 5 V VDDREG supply Variation of LVI for rising 5 V VDDREG supply before band gap trim Variation of LVI for rising 5 V VDDREG supply after band gap trim Trimming step LVI 5 V LVI 5 V hysteresis Nominal POR for rising 5 V VDDREG supply Variation of POR for rising 5 V VDDREG supply Nominal POR for falling 5 V VDDREG supply Variation of POR for falling 5 V VDDREG supply
Por3.3V_r+35% V -- V
Por3.3V_f+35% V -- Lvi5p0+6% Lvi5p0+3% -- 66 -- Por5V_r+35% -- Por5V_f+35% V V V mV mV V V V V
Lvi5p0 -- -- -- -- Por5V_r -- Por5V_f --
Using external ballast transistor. LVI for falling supply is calculated as LVI rising - LVI hysteresis. 3 Default core supply LVI guarantees only that the part will boot correctly at 20 MHz clock frequency. Before increasing operating frequency, the LVI trim must be programmed to increase the trip voltage by 80 mV.
3.6
Power Up/Down Sequencing
There is no power sequencing required among power sources during power up and power down, in order to operate within specification. Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies according to table Table 13 for all pins with pad type pad_fc (fast type), and Table 14 for all pins with pad type pad_msr_hv (medium type), pad_ssr_hv (slow type), and pad_multv_hv (multi-voltage type).
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 61
Electrical Characteristics
Table 13. Power Sequence Pin States (PAD_FC)
VDDE LOW VDDE VDDE VDDE VRC33 X LOW VRC33 VRC33 VDD X X LOW VDD pad_fc (fast) LOW HIGH HIGH IMPEDANCE FUNCTIONAL
Table 14. Power Sequence Pin States (PAD_MSR_HV / PAD_SSR_HV / PAD_MULTV_HV)
pad_msr_hv/pad_ssr_hv/pad _multv_hv (medium, slow, and multi-voltage) LOW HIGH IMPEDANCE FUNCTIONAL
VDDEH
VDD
LOW VDDEH VDDEH
X LOW VDD
3.7
DC Electrical Specifications
Table 15. DC Electrical Specifications1
Value2 Symbol Parameter Conditions min VDD VDDE VDDEH VRC33 VDDA VDDF VFLASH6 VSTBY VDDREG VDDPLL SR SR SR SR SR SR SR SR SR SR Core supply voltage I/O supply voltage I/O supply voltage 3.3 V regulated voltage3 Analog supply voltage Flash operating voltage 5 Flash read voltage SRAM standby voltage Voltage regulator supply voltage7 Clock synthesizer operating voltage -- -- -- -- -- -- -- -- -- -- 1.14 1.62 3.0 3.0 4.754 1.14 3.0 0.9 4.0 1.14 typ max 1.32 3.6 5.25 3.6 5.25 1.32 3.6 6.0 5.5 1.32 V V V V V V V V V V Unit
MPC5634M Microcontroller Data Sheet, Rev. 2 62 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 15. DC Electrical Specifications1 (continued)
Value2 Symbol Parameter Low-swing-mode8,9, 10,11 multi-voltage I/O input high voltage Low-swing-mode8,9, 10,11 multi-voltage I/O input low voltage High-swing-mode13 multi-voltage I/O input high voltage High-swing-mode multi-voltage I/O input low voltage Low-swing-mode8,9, 10,11 I/O output high voltage Low-swing-mode8,9, 10,11 I/O output low voltage High-swing-mode I/O output high voltage High-swing-mode I/O output low voltage High-swing-mode pullup current High-swing-mode pulldown current Low-swing-mode pullup current Low-swing-mode pulldown current Low-_High Swing-Mode Multi-Voltage I/O Weak Pull Up Current 35 35 25 35 25 0.8 VDDEH Conditions min VIH_LS SR Hysteresis enabled Hysteresis disabled Hysteresis enabled Hysteresis disabled Hysteresis enabled Hysteresis disabled Hysteresis enabled Hysteresis disabled 0.65 VINT12 0.55 VINT12 VSS-0.3 VSS-0.3 0.65 VDDEH 0.55 VDD VSS-0.3 VSS-0.3 2.8 V 3.1 V typ max VINT+0.312 VINT+0.312 0.35 VINT12 0.4 VINT12 VDDEH+0.3 VDD+0.3 0.35 VDDEH 0.4 VDDEH 3.7 V V V V V V Unit
VIL_LS
SR
VIH_HS
SR
VIL_HS
SR
VOH_LS
SR
VOL_LS
SR
0.2 VDDE
V
VOH_HS
SR
V
VOL_HS
SR
0.2 VDDEH
V
IPULLUP_HS IPULLDN_HS IPULLUP_LS IPULLDN_LS IPULLUP_MV
SR SR SR SR SR
135 200 135 200 175
A A A A A
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 63
Electrical Characteristics
Table 15. DC Electrical Specifications1 (continued)
Value2 Symbol Parameter Conditions min IPULLDN_MV SR Low-Swing-Mode Multi-Voltage I/O Weak Pull Down Current Fast/(low-swing-mod e multi-voltage) I/O input high voltage Fast I/O input low voltage Slow/medium/full-sw ing mode multi-voltage I/O input high voltage Slow/medium I/O input low voltage Fast I/O input hysteresis Slow/medium/multi-v oltage I/O input hysteresis Low-Swing-Mode Multi-Voltage I/O Input Hysteresis, hysteresis enabled Analog input voltage Fast/low-swing-mod e multi-voltage I/O output high voltage14,15 Slow/medium/full-sw ing-mode multi-voltage I/O output high voltage15,16 Low-Swing-Mode Multi-Voltage I/O Output High Voltage Fast I/O output low voltage14,15 Hysteresis enabled, hysteresis disabled Hysteresis enabled, hysteresis disabled Hysteresis enabled, hysteresis disabled Hysteresis enabled, hysteresis disabled -- -- 25 typ max 200 A Unit
VIH_F
SR
0.65 VDDEH 0.55 VDDEH VSS-0.3
VDDE+0.3
V
VIL_F
SR
0.35*VDDEH 0.40*VDDEH VDDEH+0.3
V
VIH_S
SR
0.65 VDDEH 0.55 VDDEH
V
VIL_S
SR
VSS-0.3
0.35*VDDEH 0.40*VDDEH 0.1 * VDDE 0.1 * VDDEH
V
VHYS_F VHYS_S
CC CC
V V
VHYS_MV
CC
--
0.25 V
V
VINDC VOH_F
SR CC
-- --
VSSA-1.0 0.8 VDDE
VDDA+1.0 --
V V
VOH_S
CC
--
0.8 VDDEH
--
V
VOH_MV
CC
Unloaded
2.7
3.7
V
VOL_F
CC
--
--
0.2*VDDE
V
MPC5634M Microcontroller Data Sheet, Rev. 2 64 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 15. DC Electrical Specifications1 (continued)
Value2 Symbol Parameter Conditions min VOL_S CC Slow/medium/multi-v oltage I/O output low voltage15,16 Low-High Swing-Mode Multi-Voltage I/O Output Low Voltage Load capacitance (fast I/O)17 -- -- typ max 0.2*VDDEH V Unit
VOL_MV
CC
--
--
0.6
V
CL
CC
DSC(PCR[8:9]) = 0b00 DSC(PCR[8:9]) = 0b01 DSC(PCR[8:9]) = 0b10 DSC(PCR[8:9]) = 0b11
-- -- -- -- -- -- --
10 20 30 50 7 10 12
pF
CIN CIN_A CIN_M
CC CC CC
Input capacitance (digital pins) Input capacitance (analog pins) Input capacitance (digital and analog pins18) Operating current 1.2 V supplies @ 80 MHz
-- -- --
pF pF pF
IDD IDDSTBY IDDSTBY150 IDDPLL
SR
VDD @1.32 V VSTBY @ 55 oC VSTBY @ 150 oC VDDPLL
-- -- -- -- -- -- --
180 100 700 15 TBD TBD 60
mA A A mA mA
IDDSLOW IDDSTOP IDD33
SR
VDD low-power mode operating current @ 1.32 V Operating current 3.3 V supplies @ 80 MHz Operating current 5.0 V supplies @ 80 MHz
Slow mode19 Stop mode20 VRC333
SR
mA
IDDA IREF IDDREG
SR
VDDA Analog reference supply current (transient) VDDREG
-- --
15.0 1.0
mA
--
70
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 65
Electrical Characteristics
Table 15. DC Electrical Specifications1 (continued)
Value2 Symbol Parameter Conditions min IDDH1 IDDH4 IDDH6 IDDH7 IDD7 IDDH9 IDD12 SR Operating current VDDE21 supplies @ 80 MHz VDDEH1 VDDEH4 VDDEH6 VDDEH7 VDDE7 VDDEH9 VDDE12 SR IACT_F Fast I/O weak pull up/down current22 1.62 V - 1.98 V 2.25 V - 2.75 V 3.0 V - 3.6 V IACT_S SR Slow/medium/multi-v oltage I/O weak pull up/down current22 I/O input leakage current23 DC injection current (per pin) Analog input current, channel off, AN[0:7], AN38, AN3924 VSS differential voltage Analog reference low voltage VRL differential voltage Analog reference high voltage 3.0 V - 3.6 V 4.5 V - 5.5 V -- -- -- -- -- -- -- -- -- -- 36 34 42 15 35 -2.5 -1.0 -250 120 139 158 95 200 2.5 1.0 250 A mA nA A A typ max See note 21 mA Unit
IINACT_D IIC IINACT_A
SR SR SR
VSS - VSSA VRL VRL - VSSA VRH
SR SR SR SR
-- -- -- --
-100 VSSA -100 VDDA-0.1
100 VSSA+0.1 100 VDDA
mV V mV V
MPC5634M Microcontroller Data Sheet, Rev. 2 66 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 15. DC Electrical Specifications1 (continued)
Value2 Symbol Parameter Conditions min VRH - VRL VSSPLL VSS TA (TL to TH) SR SR SR VREF differential voltage VSSPLL to VSS differential voltage Operating temperature range ambient (packaged) Slew rate on power supply pins -- -- -- 4.75 -100 -40.0 typ max 5.25 100 125.0 V mV
Unit
C
--
1 2
SR
--
--
50
V/ms
These specifications are design targets and subject to change per device characterization. TBD: To Be Defined. 3 These specifications apply when V RC33 is supplied externally, after disabling the internal regulator (VDDREG = 0). 4 ADC is functional with 4 V V DDA 4.75 V but with derated accuracy. This means the ADC will continue to function at full speed with no bad behavior, but the accuracy will be degraded. 5 The V DDF supply is connected to VDD in the package substrate. This specification applies to calibration package devices only. 6V FLASH is only available in the calibration package. 7 Regulator is functional, with derated performance, with supply voltage down to 4.0 V. 8 pad_multv_hv cannot be below 4.5 V when in low-swing mode. 9 The slew rate (SRC) setting must be 0b11 when in low-swing mode. 10 While in low-swing mode there are no restrictions in transitioning to high-swing mode. 11 Pin in low-swing mode can accept a 5 V input. 12 V INT refers to the internal reference voltage. For purposes of these specifications use 3.6 V for calculations. 13 Pin in low-swing mode can accept a 5 V input. 14 Simulation based capability: IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE=3.0 V; IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE=2.25 V; IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE=1.62 V 15 All VOL/VOH values 100% tested with 2 mA load. 16 Simulation based capability: IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH=4.5 V; IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH=3.0 V 17 Applies to CLKOUT, external bus pins, and Nexus pins. 18 Applies to the FCK, SDI, SDO, and SDS_B pins. 19 Bypass mode, system clock @ 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code, 4 x ADC conversion every 10 ms, 2 x PWM channels @ 1 kHz, all other modules stopped. 20 Bypass mode, system clock @ 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped. 21 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Table 16 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 22 Absolute value of current, measured at V and V . IL IH
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 67
Electrical Characteristics
23
Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. 24 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
3.7.1
I/O Pad Current Specifications
The power consumption of an I/O segment is dependent on the usage of the pin on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 16 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 16. Table 16. I/O Pad Average DC Specifications
Min. value Symbol Parameter VDDE = 5.0 V 1.14 4.5 3.0 0.65*VDDE VSS-0.3 0.55*VDDE VSS-0.3 0.1*VDDE(s) 35 35 -2.5 -150 0.8*VDDE -- 11.6 5.4 15 15 135 200 2.5 150 0.2*VDDE 40.7 21 70 95 3.0 5.5 3.6 VDDE + 0.3 0.35*VDDE VDDE + 0.3 0.40*VDDE VDDE = 3.3 V Max value VDDE = 5.0 V 1.32 3.6 VDDE = 3.3 V Unit
VDD VDDE VDD33 VIH VIL VIH VIL VHYS Pull_IOH Pull_IOL IINACT_D IINACT_A VOH VOL Ioh_msr
SR SR SR SR SR SR SR SR CC CC CC CC CC CC CC
Core supply voltage I/O supply voltage I/O pre-driver supply voltage CMOS input buffer high voltage (with hysteresis enabled) CMOS input buffer low voltage (with hysteresis enabled) CMOS input buffer high voltage (with hysteresis disabled) CMOS input buffer low voltage (with hysteresis disabled) CMOS input buffer hysteresis Weak pullup current Weak pulldown current Digital pad input leakage current (weak pull inactive) Analog pad input leakage current (weak pull inactive)) Slew rate controlled output high voltage Slew rate controlled output low voltage Pad_msr Ioh
V V V V V V V V A A A nA V V mA
MPC5634M Microcontroller Data Sheet, Rev. 2 68 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 16. I/O Pad Average DC Specifications (continued)
Min. value Symbol Parameter VDDE = 5.0 V 17.7 6.0 9.2 250 VDDE = 3.3 V 8.1 2.8 4.2 325 Max value VDDE = 5.0 V 68.2 21.3 36.3 800 VDDE = 3.3 V 38.6 11.2 20.6 1250 Unit
Iol_msr Ioh_ssr Iol_ssr Rtgate
CC CC CC CC
Pad_msr Iol Pad_ssr Ioh Pad_ssr Iol Pad_tgate_hv input resistance
mA mA mA W
3.7.2
LVDS Pad Specifications
LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is enhanced feature of the DSPI module. The LVDS pads are compliant with LVDS specification and supports data rates up to 50 MHz. Table 17. DSPI LVDS Pad Specification 1, 2
Spe c Characteristic Symbol Data Rate 4 Data Frequency FLVDSCLK Driver Specs 5 Differential output voltage VOD3 SRC=0b0 0 or 0b11 SRC=0b0 1 SRC=0b1 0 6 Common mode voltage (LVDS), VOS VOD3 SRC=0b0 0 or 0b11 SRC=0b0 1 SRC=0b1 0 7 8 9 10 Rise/Fall time Propagation delay (Low to High) Propagation delay (High to Low) Delay (H/L), sync Mode TR/TF TPLH TPHL tPDSYNC 150 120 180 1.075 0.86 1.29 2 4 4 4 1.2 400 320 480 1.325 1.06 1.59 ns ns ns ns V mV 50 MHz Min. Value Typ. Value Max. Value Unit
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 69
Electrical Characteristics
Table 17. DSPI LVDS Pad Specification 1, 2 (continued)
11 12 Delay, Z to Normal (High/Low) Diff Skew Itphla-tplhbI or Itplhb-tphlaI TDZ TSKEW Termination 13 14
1 2
500 0.5
ns ns
Trans. Line (differential Zo) Temperature
95 -40
100
105 150
W C
These are typical values that are estimated from simulation. These specifications are subject to change per device characterization. 3 Preliminary target values. Actual specifications to be determined.
3.8
Oscillator and PLLMRFM Electrical Characteristics
Table 18. PLLMRFM Electrical Specifications1
(VDDPLL = 3.0 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) Value Symbol Parameter PLL reference frequency range2 Conditions min fref_crystal fref_ext CC Crystal reference External reference fpll_in fvco fsys fsys CC CC CC CC Phase detector input frequency range (after pre-divider) VCO frequency range On-chip PLL frequency2 System frequency in bypass mode3 -- -- -- Crystal reference External reference tCYC fLORL fLORH fSCM CC CC System clock period Loss of reference frequency window4 -- Lower limit Upper limit CC Self-clocked mode frequency 5,6 -- 4 4 4 256 16 4 0 -- 1.6 24 1.2 max 20 80 16 512 80 20 80 1 / fsys 3.7 56 75 MHz ns MHz MHz MHz MHz MHz MHz Unit
MPC5634M Microcontroller Data Sheet, Rev. 2 70 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 18. PLLMRFM Electrical Specifications1
(VDDPLL = 3.0 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued) Value Symbol Parameter Conditions min CJITTER CC CLKOUT period jitter7,8,9,10 Peak-to-peak (clock edge to clock edge) Long-term jitter (avg. over 2 ms interval) tcst VIHEXT CC CC Crystal start-up time 11, 12 EXTAL input high voltage -- Crystal Mode13 External Reference13, 14 VILEXT CC EXTAL input low voltage Crystal Mode13 External Reference13, 14 -- tlpll tdc fLCK fUL fCS fDS fMOD
1 2 3 4 5 6 7 8
Unit max 5 % fCLKOUT
fSYS maximum
-5
-6
6
ns
-- Vxtal + 0.4 VRC33/2 + 0.4 -- 0 5 -- 40 -6 -18 0.25 -0.5 --
10 -- VRC33 Vxtal 0.4 VRC33/2 - 0.4 30 200 60 6 18 4.0 -8.0 100
ms V
V
CC CC CC CC CC CC
XTAL load capacitance11 PLL lock time
11, 15
-- -- -- -- -- Center spread Down Spread
pF s % % fsys % fsys %fsys
Duty cycle of reference Frequency LOCK range Frequency un-LOCK range Modulation Depth
CC
Modulation frequency16
--
kHz
All values given are initial design targets and subject to change. Considering operation with PLL not bypassed. All internal registers retain data at 0 Hz. "Loss of Reference Frequency" window is the reference frequency range outside of which the PLL is in self clocked mode. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR window. fVCO self clock range is 20-150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced mode. This value is determined by the crystal manufacturer and board design. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval.
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 71
Electrical Characteristics
9
Proper PC board layout procedures must be followed to achieve specifications. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this PLL, load capacitors should not exceed these limits. 12 Proper PC board layout procedures must be followed to achieve specifications. 13 This parameter is guaranteed by design rather than 100% tested. 14 VIHEXT cannot exceed VRC33 in external reference mode. 15 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 16 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50kHz.
10
3.9
eQADC Electrical Characteristics
Table 19. eQADC Conversion Specifications (operating)
Value Symbol Parameter min fADCLK CC TSR -- INL8 INL16 DNL8 DNL16 OFFNC OFFWC GAINNC GAINWC IINJ EINJ TUE8 TUE16
1
Unit max 16 128+14 -- -- 44 84 34 84 1004 44 04 44 1 + 44 + 44,6 +8 MHz ADCLK cycles s mV LSB5 LSB LSB LSB LSB LSB LSB LSB mA Counts Counts Counts
CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC
ADC clock (ADCLK) frequency Conversion cycles Stop mode recovery time1 Resolution2 INL: 8 MHz ADC clock3 INL: 16 MHz ADC clock3 DNL: 8 MHz ADC clock3 DNL: 16 MHz ADC clock3 Offset error without calibration Offset error with calibration Full scale gain error without calibration Full scale gain error with calibration Disruptive input injection current 6, 7, 8, 9 Incremental error due to injection current10,11 TUE value at 8 MHz TUE value at 16 MHz
2 2+13 10 1.25 -44 -84 -34 -84 0
4
-44 -1204 -44 -1 -- -- --
Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms. 2 At VRH - VRL = 5.12 V, one count = 1.25 mV. Without using pregain. 3 INL and DNL are tested from V RL + 50 LSB to VRH - 50LSB. 4 New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully included.
MPC5634M Microcontroller Data Sheet, Rev. 2 72 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
5 6
At VRH - VRL = 5.12 V, one LSB = 1.25 mV. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater then VRH and $000 for values less then VRL. Other channels are not affected by non-disruptive conditions. 7 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 8 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = - 0.3 V, then use the larger of the calculated values. 9 Condition applies to two adjacent pins at injection limits. 10 Performance expected with production silicon. 11 All channels have same 10 k < Rs < 100 k; Channel under test has Rs=10 k; IINJ=IINJMAX,IINJMIN
3.10
Platform Flash Controller Electrical Characteristics
Table 20. APC, RWSC, WWSC Settings vs. Frequency of Operation1
Target Max Frequency (MHz) 30 60 80 All
1 2
APC2 000 001 010 111
RWSC2 000 001 010 111
WWSC 01 01 01 11
Illegal combinations exist, all entries must be taken from the same row APC must be equal to RWSC
3.11
Num 1 2 3 4 5 6 7
1
Flash Memory Electrical Characteristics
Table 21. Flash Program and Erase Specifications1
Symbol Tdwprogram Tpprogram T16kpperase T48kpperase T64kpperase T128kpperase T256kpperase CC CC CC CC CC CC CC Parameter Double Word (64 bits) Program Time Page Program Time 16 KB Block Pre-program and Erase Time 48 KB Block Pre-program and Erase Time 64 KB Block Pre-program and Erase Time 128 KB Block Pre-program and Erase Time 256 KB Block Pre-program and Erase Time Min. Value -- -- -- -- -- -- -- Typical Value -- -- -- -- -- -- -- Initial Max2 444 500 750 900 1300 2100 Max3 500 500 5000 5000 5000 7500 10000 Unit s s ms ms ms ms ms
Typical program and erase times assume nominal supply values and operation at 25 oC. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 oC, typical supply voltage, 80MHz minimum system frequency. 3 The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. 4 Page size is 128 bits (4 words).
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 73
Electrical Characteristics
Table 22. Flash EEPROM Module Life
Value1 Symbol Parameter Conditions min P/E CC Number of program/erase cycles per block for 16 Kbyte, 48 Kbyte, and 64 Kbyte blocks over the operating temperature range (TJ) Number of program/erase cycles per block for 128 Kbyte and 256 Kbyte blocks over the operating temperature range (TJ) Minimum data retention at 150 C -- 100,000 typ cycles Unit
P/E
CC
--
1,000
100,000
cycles
Retention
CC
Blocks with 0 - 1,000 P/E cycles Blocks with 1,001 - 100,000 P/E cycles
20 1-5 (TBD)
-- --
years
1
TBD: To Be Defined.
3.12
3.12.1
AC Specifications
Pad AC Specifications
Table 23. Pad AC Specifications (5.0 V, 1.8 V)1,2
Output Delay (ns)3,4 Low-to-High / High-to-Low
Name
Rise/Fall Edge (ns)4,5 Min
2.2/2.2 9/9 N/A
Drive Load (pF)
50 200
SRC/DSC MSB,LSB 119 1010
Min
4.7/4.2 14/13
Max
12/11 32/34
Max
5.3/5.9 21/23
pad_msr_hv6,7,8
8.6/14 18/26 64/77 89/101 7.4/6.8 9.2/8.1
20/35 41/64 142/186 195/253 18/18 27/28
4/6.8 11/14 32/39 44/51 4.4/4.3 5.5/5.1 N/A
8.7/16.6 24/35 65/89 91/122 10/11 15/17
50 01 200 50 00 200 50 200 1010 119
pad_ssr_hv8,11
26/26 31/31 137/139 163/167
61/67 80/90 318/343 408/431
13/13 15/15 72/74 80/82
30/34 38/44 155/173 188/204
50 01 200 50 00 200
MPC5634M Microcontroller Data Sheet, Rev. 2 74 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 23. Pad AC Specifications (5.0 V, 1.8 V)1,2 (continued)
Output Delay (ns)3,4 Low-to-High / High-to-Low
Name
Rise/Fall Edge (ns)4,5 Min Max
5.7/5.6 TBD N/A
Drive Load (pF)
30 200
SRC/DSC MSB,LSB 119 1010
Min
Max
3.7/3.1 TBD
pad_multv_hv (High Swing Mode)
8,12
32 72 210 295
15/15 38/46 100/100 134/134 5.4/4.8 0.3/0.3 1.5/1.5 5000/5000
50 01 200 50 00 200 30pF 0.5 50 119 N/A N/A
pad_multv_hv (Low Swing Mode) pad_i_hv13 pull_hv
1
7.4/6.1 0.5/0.5 NA 1.9/1.9 6000
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDE = 1.62 V to 1.98 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH. 2 TBD: To Be Defined. 3 This parameter is supplied for reference and is not guaranteed by design and not tested. 4 Delay and rise/fall are measured to 20% or 80% of the respective signal. 5 This parameter is guaranteed by characterization before qualification rather than 100% tested. 6 In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads 7 Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown. 8 Output delay is shown in Figure 8. Add a maximum of one system clock to the output delay for delay with respect to system clock. 9 Can be used on the tester 10 This drive select value is not supported. If selected, it will be approximately equal to 11. 11 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown. 12 Selectable high/low swing IO pad with selectable slew in high swing mode only. 13 Stand alone input buffer. Also has weak pull-up/pull-down.
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 75
Electrical Characteristics
Table 24. Pad AC Specifications (3.3 V, 3.3 V)1
Output Delay (ns)2,3 Low-to-High / High-to-Low Min pad_msr_hv
5,6,7
Rise/Fall Edge (ns)3,4 Min 2.8/2.6 11.3/10.4 N/A Max 7.6/8.9 30/35
Pad Type
Drive Load (pF) 50 200
SRC/DSC MSB,LSB 118
Max 18/17 46/51
5.8/5 17/15
109 11.8/21.8 34/49 79/107 114/153 15/17 57/67 50 200 50 200 50 200 109 38/44 82/96 188/204 250/288 5.7/5.6 50 200 50 200 30 200 N/A 109 15/15 38/46 100/100 134/134 5.4/4.8 NA NA NA NA NA NA NA 50 200 50 200 30pf NA NA NA NA NA NA NA 0.5 50 N/A N/A 00 01 10 118 00 01 118 00 01 11 00 01
10/17 22/30 78/94 107/123 pad_ssr_hv
7,10
28/47 58/88 184/240 253/330 27/28 81/92
4.7/7.7 13/16 36/44 50/57 13.4/15.5 22/20 N/A
9.2/8.1 30/28
31/31 58/56 163/167 216/216 pad_multv_hv7,11 (High Swing Mode)
80/90 146/167 408/431 533/592 3.7/3.1
15.4/15.4 33/31 80/82 106/105
32 72 210 295 pad_multv_hv7,11 (Low Swing Mode) 7.4/6.1 NA NA NA NA NA NA NA pad_i_hv12 pull_hv
1
0.5/0.5 NA
3/3 6000
0.4/0.4
1.5/1.5 5000/5000
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDE = 3 V to 3.6 V, VDDEH = 3 V to 3.6 V, TA = TL to TH.
MPC5634M Microcontroller Data Sheet, Rev. 2 76 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2 3
This parameter is supplied for reference and is not guaranteed by design and not tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. 4 This parameter is guaranteed by characterization before qualification rather than 100% tested. 5 In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads 6 Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown. 7 Output delay is shown in Figure 8. Add a maximum of one system clock to the output delay for delay with respect to system clock. 8 Can be used on the tester 9 This drive select value is not supported. If selected, it will be approximately equal to 11. 10 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown. 11 Selectable high/low swing IO pad with selectable slew in high swing mode only. 12 Stand alone input buffer. Also has weak pull-up/pull-down.
VDDE/2 Pad Data Input
Rising Edge Output Delay
Falling Edge Output Delay VOH
Pad Output Figure 8. Pad Output Delay
VOL
3.13
3.13.1
AC Timing
IEEE 1149.1 Interface Timing
Table 25. JTAG Pin AC Electrical Characteristics1
Num 1 2 3 4 5 Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH CC CC CC CC CC Characteristic TCK Cycle Time TCK Clock Pulse Width TCK Rise and Fall Times (40% - 70%) TMS, TDI Data Setup Time TMS, TDI Data Hold Time Min. Value 100 40 5 25 Max. Value -- 60 3 -- -- Unit ns ns ns ns ns
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 77
Electrical Characteristics
Table 25. JTAG Pin AC Electrical Characteristics1 (continued)
Num 6 7 8 9 10 11 12 13 14 15
1
Symbol tTDOV tTDOI tTDOHZ tJCMPPW tJCMPS tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT CC CC CC CC CC CC CC CC CC CC
Characteristic TCK Low to TDO Data Valid TCK Low to TDO Data Invalid TCK Low to TDO High Impedance JCOMP Assertion Time JCOMP Setup Time to TCK Low TCK Falling Edge to Output Valid TCK Falling Edge to Output Valid out of High Impedance TCK Falling Edge to Output High Impedance Boundary Scan Input Valid to TCK Rising Edge TCK Rising Edge to Boundary Scan Input Invalid
Min. Value 0 100 40 -- -- 50 50
Max. Value 20 -- 20 -- -- 50 50 50 -- --
Unit ns ns ns ns ns ns ns ns ns ns
JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to Low-Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 26 for functional specifications.
TCK 2 3 2
1
3
Figure 9. JTAG Test Clock Input Timing
MPC5634M Microcontroller Data Sheet, Rev. 2 78 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
TCK
4 5
TMS, TDI
6 7 8
TDO
Figure 10. JTAG Test Access Port Timing
TCK 10 JCOMP
9
Figure 11. JTAG JCOMP Timing
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 79
Electrical Characteristics
TCK 11 13
Output Signals
12
Output Signals 14 15
Input Signals
Figure 12. JTAG Boundary Scan Timing
3.13.2
Num 1 2 3 4 6 7 8 9 10
Nexus Timing
Table 26. Nexus Debug Port Timing1
Symbol tMCYC tMDC tMDOV tMSEOV tEVTOV tEVTIPW tEVTOPW tTCYC tTDC CC CC CC CC CC CC CC CC CC Characteristic MCKO Cycle Time MCKO Duty Cycle MCKO Low to MDO Data Valid
4
Min. Value 22,3 40 - 0.1 0.1 - 0.1 4.0 1 45 6 40
Max. Value 8 60 0.2 0.2 0.2 60
Unit tCYC % tMCYC tMCYC tMCYC tTCYC tMCYC tCYC %
MCKO Low to MSEO Data Valid4 MCKO Low to EVTO Data Valid4 EVTI Pulse Width EVTO Pulse Width TCK Cycle Time TCK Duty Cycle
MPC5634M Microcontroller Data Sheet, Rev. 2 80 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 26. Nexus Debug Port Timing1 (continued)
Num 11 12 13 14 15 16
1
Symbol tNTDIS tNTDIH tNTMSS tNTMSH tJOV CC CC CC CC CC CC
Characteristic TDI Data Setup Time TDI Data Hold Time TMS Data Setup Time TMS Data Hold Time TCK Low to TDO Data Valid RDY Valid to MCKO7
Min. Value 5 25 5 25 10 -
Max. Value 20 -
Unit ns ns ns ns ns -
2 3 4 5
6 7
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to Low-Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10. Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV] depending on the actual system frequency being used. This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum MCKO period specification. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum TCK period specification. The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly. 1 2 MCKO 3 4 6 MDO MSEO EVTO Output Data Valid
Figure 13. Nexus Output Timing
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 81
Electrical Characteristics
TCK EVTI EVTO
9
7 8
7 8
Figure 14. Nexus Event Trigger and Test Clock Timings
TCK 11 13 12 14
TMS, TDI
15
TDO
Figure 15. Nexus TDI, TMS, TDO Timing
MPC5634M Microcontroller Data Sheet, Rev. 2 82 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
3.13.3
Calibration Bus Interface Timing
Table 27. Calibration Bus Operation Timing 1
66 MHz (ext. bus)2
Num 1
Symbol TC
Characteristic Min Max 15.2
Unit ns
Notes Signals are measured at 50% VDDE.
CC CLKOUT Period
2 3 4 5
tCDC tCRT tCFT tCOH
CC CLKOUT duty cycle CC CLKOUT rise time CC CLKOUT fall time CC CLKOUT Posedge to Output Signal Invalid or High Z(Hold Time) ADDR[8:31] CS[0:3] DATA[0:31] OE RD_WR TS WE[0:3]/BE[0:3]
45% 1.04/1.5
55%
3 3
TC ns ns ns Hold time selectable via SIU_ECCR[EBTS] bit: EBTS=0: 1.0ns EBTS=1: 1.5ns
-
6
tCOV
CC CLKOUT Posedge to Output Signal Valid (Output Delay) ADDR[8:31] CS[0:3] DATA[0:31] OE RD_WR TS WE[0:3]/BE[0:3]
-
6.04/7.0
ns
Output valid time selectable via SIU_ECCR[EBTS] bit: EBTS=0: 5.5ns EBTS=1: 6.5ns
7
tCIS
CC Input Signal Valid to CLKOUT Posedge (Setup Time) DATA[0:31]
5.0
-
ns
8
tCIH
CC CLKOUT Posedge to Input Signal Invalid (Hold Time) DATA[0:31]
1.0
-
ns
9 10
1 2 3 4 5
tAPW tAAI
CC ALE Pulse Width5 CC ALE Negated to Address Invalid5
6.5 3
-
ns ns
Calibration bus timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDE = 1.6 V to 3.6 V (unless stated otherwise), TA = TL to TH, and CL = 30 pF with DSC = 0b10. The external bus is limited to half the speed of the internal bus. The maximum external bus frequency is 66 MHz. Refer to Fast Pad timing in Table 23 and Table 24 (different values for 1.8 V vs. 3.3 V). The EBTS=0 timings are only valid/ tested at VDDE=2.25-3.6 V, whereas EBTS=1 timings are valid/tested at 1.6-3.6 V. Measured at 50% of ALE.
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 83
Electrical Characteristics
Voh_f VDDE/2 Vol_f 3 2 2 4 1
CLKOUT
Figure 16. CLKOUT Timing
CLKOUT
VDDE/2
6 5 5 VDDE/2
OUTPUT BUS
VDDE/2
6 5 5
OUTPUT SIGNAL
VDDE/2
6
OUTPUT SIGNAL
VDDE/2
Figure 17. Synchronous Output Timing
MPC5634M Microcontroller Data Sheet, Rev. 2 84 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
CLKOUT
VDDE/2
7 8
INPUT BUS
VDDE/2
7 8
INPUT SIGNAL
VDDE/2
Figure 18. Synchronous Input Timing
ipg_clk CLKOUT ALE TS A/D ADDR 9 10 DATA
Figure 19. ALE Signal Timing
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 85
Electrical Characteristics
3.13.4
eMIOS Timing
Table 28. eMIOS Timing1
Max. Value -
Num 1 2
1
Symbol tMIPW tMOPW
Characteristic CC eMIOS Input Pulse Width CC eMIOS Output Pulse Width
Min. Value 4 1
Unit tCYC tCYC
eMIOS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00.
3.13.5
DSPI Timing
Table 29. DSPI Timing1,2
40 MHz 60 MHz Min. 28.4 ns 26 25 (1/2tSC) -2 -- Max. 3.5 ms -- -- (1/2tSC) +2 25 80 MHz Unit Min. Max. 5.8 ms -- -- (1/2tSC) +2 25 Min. 24.4 ns 22 21 (1/2tSC) -2 -- Max. 2.9 ms -- -- (1/2tSC) +2 25 -- ns ns ns ns
Num
Symbol
Characteristic SCK Cycle Time3,4 PCS to SCK Delay5 After SCK Delay6 SCK Duty Cycle Slave Access Time (SS active to SOUT driven) Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) PCSx to PCSS time PCSS to PCSx time
1 2 3 4 5
tSCK tCSC tASC tSDC tA
CC CC CC CC CC
48.8 ns 46 45 (1/2tSC) -2 --
6
tDIS
CC
--
25
--
25
--
25
ns
7 8 9
tPCSC tPASC tSUI
CC CC CC
4 5
-- --
4 5
-- --
4 5
-- --
ns ns
Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)7 Master (MTFE = 1, CPHA = 1) 20 2 -4 20 -- -- -- -- 20 2 6 20 -- -- -- -- 20 2 8 20 -- -- -- -- ns
MPC5634M Microcontroller Data Sheet, Rev. 2 86 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 29. DSPI Timing1,2 (continued)
40 MHz Num Symbol Characteristic Min. 10 tHI CC Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)7 Master (MTFE = 1, CPHA = 1) 11 tSUO CC Master (MTFE = 0) Slave Master (MTFE = 1, CPHA=0) Master (MTFE = 1, CPHA=1) 12 tHO CC Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1)
1
60 MHz Min. Max.
80 MHz Unit Min. Max.
Max.
Data Hold Time for Inputs -4 7 45 -4 -- -- -- -- -4 7 25 -4 -- -- -- -- -4 7 21 -4 -- -- -- -- ns
Data Valid (after SCK edge) -- -- -- -- 5 25 45 5 -- -- -- -- 5 25 25 5 -- -- -- -- 5 25 21 5 ns
Data Hold Time for Outputs -5 5.5 8 -5 -- -- -- -- -5 5.5 4 -5 -- -- -- -- -5 5.5 3 -5 -- -- -- -- ns
2
3 4 5 6 7
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0-5.25 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11. Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 62 MHz parts allow for a 60 MHz system clock + 2% FM, and 82 MHz parts allow for 80 MHz system clock + 2% FM. The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two MPC5634M devices communicating over a DSPI link. The actual minimum SCK cycle time is limited by pad performance. The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 87
Electrical Characteristics
2 PCSx 4 SCK Output (CPOL=0) 4 1
3
SCK Output (CPOL=1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data
First Data
Figure 20. DSPI Classic SPI Timing - Master, CPHA = 0
PCSx
SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Figure 21. DSPI Classic SPI Timing - Master, CPHA = 1
MPC5634M Microcontroller Data Sheet, Rev. 2 88 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2 SS 1 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4
3
6
Last Data
First Data
Last Data
Figure 22. DSPI Classic SPI Timing - Slave, CPHA = 0
SS
SCK Input (CPOL=0)
SCK Input (CPOL=1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 23. DSPI Classic SPI Timing - Slave, CPHA = 1
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 89
Electrical Characteristics
3 PCSx 4 2 SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1
10
Figure 24. DSPI Modified Transfer Format Timing - Master, CPHA = 0
PCSx
SCK Output (CPOL=0)
SCK Output (CPOL=1) 9 SIN First Data Data 12 SOUT First Data Data 10
Last Data 11 Last Data
Figure 25. DSPI Modified Transfer Format Timing - Master, CPHA = 1
MPC5634M Microcontroller Data Sheet, Rev. 2 90 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
SS
2 1
3
SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4
Figure 26. DSPI Modified Transfer Format Timing - Slave, CPHA =0
SS
SCK Input (CPOL=0)
SCK Input (CPOL=1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 27. DSPI Modified Transfer Format Timing - Slave, CPHA =1
7 PCSS PCSx 8
Figure 28. DSPI PCS Strobe (PCSS) Timing
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 91
Electrical Characteristics
3.13.6
eQADC SSI Timing
Table 30. eQADC SSI Timing Characteristics (pads at 3.3 V or at 5.0 V)1
CLOAD = 25pF on all outputs. Pad drive strength set to maximum.
Num 1 1 2 3 4 5 6 7 8
1
Symbol fFCK tFCK tFCKHT tFCKLT CC CC CC CC
Rating FCK Frequency 2, 3 FCK Period (tFCK = 1/ fFCK) Clock (FCK) High Time Clock (FCK) Low Time SDS Lead/Lag Time SDO Lead/Lag Time Data Valid from FCK Falling Edge (tFCKLT+tSDO_LL) eQADC Data Setup Time (Inputs) eQADC Data Hold Time (Inputs)
Min 1/17 2 tSYS_CLK - 6.5 tSYS_CLK - 6.5 -7.5 -7.5 1 22 1
Typ
Max 1/2 17
9* tSYS_CLK + 8* tSYS_CLK +
Unit fSYS_CLK tSYS_CLK 6.5 6.5 ns ns ns ns ns ns ns
tSDS_LL CC tSDO_LL CC tDVFE tEQ_SU CC CC
+7.5 +7.5
tEQ_HO CC
SS timing specified at FSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00. 2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays. 3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
1 2 FCK 4 SDS
25th 2nd 26th
3
4
5 SDO External Device Data Sample at FCK Falling Edge
6
1st (MSB)
5
8 7 SDI eQADC Data Sample at FCK Rising Edge
1st (MSB) 2nd 25th 26th
Figure 29. eQADC SSI Timing
MPC5634M Microcontroller Data Sheet, Rev. 2 92 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
4
4.1
Mechanical Outline Drawings
100 LQFP
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 93
Mechanical Outline Drawings
Figure 30. 100 LQFP Package Mechanical Drawing (part 1)
MPC5634M Microcontroller Data Sheet, Rev. 2 94 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
Figure 31. 100 LQFP Package Mechanical Drawing (part 2)
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 95
Mechanical Outline Drawings
Figure 32. 100 LQFP Package Mechanical Drawing (part 3)
MPC5634M Microcontroller Data Sheet, Rev. 2 96 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
4.2
144 LQFP
Figure 33. 144 LQFP Package Mechanical Drawing (part 1)
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 97
Mechanical Outline Drawings
Figure 34. 144 LQFP Package Mechanical Drawing (part 2)
MPC5634M Microcontroller Data Sheet, Rev. 2 98 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
Figure 35. 144 LQFP Package Mechanical Drawing (part 3)
4.3
176 LQFP
MPC5634M Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary--Subject to Change Without Notice
99
Mechanical Outline Drawings
Figure 36. 176 LQFP Package Mechanical Drawing (part 1)
MPC5634M Microcontroller Data Sheet, Rev. 2 100 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
Figure 37. 176 LQFP Package Mechanical Drawing (part 2)
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 101
Mechanical Outline Drawings
Figure 38. 176 LQFP Package Mechanical Drawing (part 3)
MPC5634M Microcontroller Data Sheet, Rev. 2 102 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanical Outline Drawings
4.4
208 MAPBGA
Figure 39. 208 MAPBGA Package Mechanical Drawing (part 1)
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 103
Mechanical Outline Drawings
Figure 40. 208 MAPBGA Package Mechanical Drawing (part 2)
MPC5634M Microcontroller Data Sheet, Rev. 2 104 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Ordering Information
5
Ordering Information
Table 31. Orderable Part Number Summary
Part Number MPC5632MMLQ60 MPC5632MMLL60 MPC5632MMLQ40 MPC5632MMLL40 MPC5633MMMG80 MPC5633MMLU80 MPC5633MMLQ80 MPC5633MMLL80 MPC5633MMMG60 MPC5633MMLU60 MPC5633MMLQ60 MPC5633MMLL60 MPC5633MMLQ40 MPC5633MMLL40 MPC5634MMMG80 MPC5634MMLU80 MPC5634MMLQ80 MPC5634MMMG60 MPC5634MMLU60 MPC5634MMLQ60 Flash/SRAM (Kbytes) 768 / 48 768 / 48 768 / 48 768 / 48 1024 / 64 1024 / 64 1024 / 64 1024 / 64 1024 / 64 1024 / 64 1024 / 64 1024 / 64 1024 / 64 1024 / 64 1536 / 94 1536 / 94 1536 / 94 1536 / 94 1536 / 94 1536 / 94 Package 144 LQFP Pb-free 100 LQFP Pb-free 144 LQFP Pb-free 100 LQFP Pb-free 208 MAPBGA Pb-free 176 LQFP Pb-free 144 LQFP Pb-free 100 LQFP Pb-free 208 MAPBGA Pb-free 176 LQFP Pb-free 144 LQFP Pb-free 100 LQFP Pb-free 144 LQFP Pb-free 100 LQFP Pb-free 208 MAPBGA Pb-free 176 LQFP Pb-free 144 LQFP Pb-free 208 MAPBGA Pb-free 176 LQFP Pb-free 144 LQFP Pb-free Speed (MHz) 60 60 40 40 80 80 80 80 60 60 60 60 40 40 80 80 80 60 60 60
Table 31 shows the orderable part numbers for the MPC5634M series.
MPC5634M Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 105
Ordering Information
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Rev. 2 December 9, 2008 3:18 pm Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2008. All rights reserved.
MPC5634M Microcontroller Data Sheet, Rev. 2 106 Preliminary--Subject to Change Without Notice Freescale Semiconductor

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